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Dynamic Engineering News
12/2024 Updated Design PCIe-Spartan-VI Windows® 10/11 package . Updated software package now supports on-the-fly programming and verification of the User FPGA under SW control. Update the BIT file in the FPGA without cables etc. Reconfigurability allows the design to be adapted to current conditions in near real time. Default programs can be programmed into the User FPGA QSPI support FLASH - for near instant on availability.
More about PCIe-Spartan-VI: User programmable Spartan VI FPGA supported with 16 DMA ports, 40 Differential IO [LVDS and or RS-485], 12 TTL, 8 PLLs with 3 clock references each. Windows SW package includes User R/W functions to control the user design plus built in features with dedicated SW. The Bus FPGA handles the host interface and provides a General Purpose 32 bit 50 MHz bus to the User FPGA plus 8 channels with Rx and Tx lanes between the Bus and User FPGAs. The lanes are byte wide and have flow control built in. SW support for DMA operation to use with the User FPGA via the byte lanes. QSPI for User image. SW based JTAG load of User FPGA in next software release. Industrial temperature components. IO supported with D100 connector. Same pinout as PCIe-AlteraCycloneIV design. Reference VHDL project available for User FPGA.
Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
11/2024 Updated Driver and PCB Updated IO interface now uses FETs to allow up to 50V IO and up to 200 mA sink per transmit line. Each Input line now uses a series resistor and zener diode to allow a wide range - TTL - 50V on the input lines. The IP-Parallel-HV and IP-Parallel-HV-Test models have been combined. Addresses for the base model remain the same. Updated Win10 driver and reference SW package included with purchase. Test features added include controlling the second interrupt line, memory implemented in the memory space, and Address capture to support testing IP Module Carriers and developing drivers. The same PCB is utilized for IP-Parallel-HV-Miller [implements Miller encoding/decoding. Similar to Manchester], IP-HaveQuick[Time of Day receiver / transmitter utilizing HQT Manchester encoded data], and IP-Crypto[Interface with KYK-13 to read the key]. Use the manuals tab to navigate to the user manual for more detail.
10/2024 Updated Design PMC2PCI has been updated to support continued manufacture. Passive design with 32-64 bit operation depending on carrier installed into. 25-66 MHz clock rates, 5V and 3.3V keyed slots - actual PCI voltage determined by carrier. One slot available at a time. Install a PCI device into a PMC position. Right angle mounting available for parallel PCI and PMC installation.
09/2024 Updated SpaceWire Monitor with more memory and two added ports by Dynamic Engineering.. SpaceWire Monitor can be used to capture the communication between two SpaceWire nodes as well as provide two standard SpaceWire nodes with all of the features of our BK models. For the monitor ports, both sides are captured, filtered and stored to memory. Data is stored by packet and each packet is pre-pended with time, number and size. SpaceWire-Monitor can capture the data needed to do system / platform validation, debug tricky communications issues, capture HW data errors and more. Software currently executes with Linux and Windows®. SpaceWire-Monitor is a build option for PCI, PCIe, PMC, PC104p, and PCI-104 models of SpaceWire IO. All models offered have 32 MegaBytes of storage per port. DMA transfers data to the user specified file. NVMe or HDD with cache recommended for file storage. Data is stored as binary. Application includes binary conversion utility to provide human readable files. Click below for the SpaceWire-Monitor data page. Use the manuals tab to navigate to the user manual for more detail.
8/2024 Updated Design ccXMC-Serial has been updated with additional functionality. The new features include programmable active edge, CRC algorithm, clock count for HDLC and programmable clock burst for NRZ.. The base features include Spartan 6 FPGA, DDR, PLL, temperature sensor, 16 RS-485/LVDS transceivers, and 3 ports with programmable RS-232/RS-485 suitable for UARTs and similar. ccXMC-Serial is a conduction cooled XMC implementation. The IO is assigned to be compliant with SOSA requirements utilizing the Pn6 rear IO connector. The first design implemented on this platform is ccXMC-Serial-HDLC. 2 ports of HDLC, 2 ports of NRZL, and 3 ports of UART are implemented in this design. Windows drivers and reference SW currently available. HDLC and NRZL are supported with RS-485 transceivers.
HDLC is programmable for length, speed, internal or external clock reference, active edge, CRC algorithm [plus initial pattern, final inversion, check value]. The CRC is calculated and checked in hardware. The supporting memory is dual port RAM organized as a circular buffer to allow retransmisison of messages.
NRZL is programmable for length, LSB or MSB first, inversion etc. Rate of transmission and gaps between data sent are also programmable, New feature of burst count within a message.
UARTs are programmable for 7/8 bits, 1/2 stop bits, odd/even/no parity, transmission rate, and several modes of operation including unpacked [8 bit data], packed [32 bit data], packetized[programmable length per message], as well as gaps between packets and more.
Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
7/2024 Updated Designs PMC-SpaceWire-BK, PCI-SpaceWire-BK , and PC104p-SpaceWire-BK PCBs and Linux packages have been updated. PMC-SpaceWire-BK, PCI-SpaceWire, and PC104p-SpaceWire join PCIe-SpaceWire-BK featuring enhanced DDR based memory with a default allocation or 32 Mbytes per port. The standard features are retained. PMC-SpaceWire-BK, PCIe-SpaceWire-BK as well as the other models implement SpaceWire [ECSS-E-ST-50-12C specification] in a convenient format. Four fully independent and highly programmable SpaceWire ports are provided by the SpaceWire-BK design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Rx ports autobaud. First character synchronization. The Win10/11 and Linux software packages support all of the features of the SpaceWire-BK design, and the UserAp reference software demonstrates the features including: internal and external loop-back with and without DMA operation. For example, several frequency files are provided and the UserAp software can automatically load them for you. Set any port to any programmable frequency. The Win10 and Linux packages are included with your purchase of SpaceWire-BK models. Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
5/2024 New Design PCIe-Spartan-VI is now available. User programmable Spartan VI FPGA supported with 16 DMA ports, 40 Differential IO [LVDS and or RS-485], 12 TTL, 8 PLLs with 3 clock references each. Windows SW package includes User R/W functions to control the user design plus built in features with dedicated SW. The Bus FPGA handles the host interface and provides a General Purpose 32 bit 50 MHz bus to the User FPGA plus 8 channels with Rx and Tx lanes between the Bus and User FPGAs. The lanes are byte wide and have flow control built in. SW support for DMA operation to use with the User FPGA via the byte lanes. QSPI for User image. SW based JTAG load of User FPGA in next software release. Industrial temperature components. IO supported with D100 connector. Same pinout as PCIe-AlteraCycloneIV design. Reference VHDL project available for User FPGA.
Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
5/2024 New Design ccXMC-Serial is now available. The base features include Spartan 6 FPGA, DDR, PLL, temperature sensor, 16 RS-485/LVDS transceivers, and 3 ports with programmable RS-232/RS-485 suitable for UARTs and similar. ccXMC-Serial is a conduction cooled XMC implementation. The IO is assigned to be compliant with SOSA utilizing the Pn6 rear IO connector. The first design implemented on this platform is ccXMC-Serial-HDLC. 2 ports of HDLC, 2 ports of NRZL, and 3 ports of UART are implemented in this design. Windows drivers and reference SW currently available. HDLC and NRZL are supported with RS-485 transceivers.
HDLC is programmable for length, speed, internal or external clock reference. The CRC is calculated and checked in hardware. The supporting memory is dual port RAM organized as a circular buffer to allow retransmisison of messages.
NRZL is programmable for length, LSB or MSB first, inversion etc. Rate of transmission and gaps between data sent are also programmable,
UARTs are programmable for 7/8 bits, 1/2 stop bits, odd/even/no parity, transmission rate, and several modes of operation including unpacked [8 bit data], packed [32 bit data], packetized[programmable length per message], as well as gaps between packets and more.
Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
3/2024 Updated Design PCIe-SpaceWire-BK PCB and Windows package Has been updated. Now featuring enhanced DDR based memory with a default allocation or 32 Mbytes per port. The standard features are retained. PCIe-SpaceWire-BK as well as the other models implement SpaceWire [ECSS-E-ST-50-12C specification] in a convenient format. Four fully independent and highly programmable SpaceWire ports are provided by the SpaceWire-BK design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Rx ports autobaud. First character synchronization. The Win10/11 software package supports all of the features of the SpaceWire-BK design, and the UserAp reference software demonstrates the features including: internal and external loop-back with and without DMA operation. For example, several frequency files are provided and the UserAp software can automatically load them for you. Set any port to any programmable frequency. The Win10 package is included with your purchase of SpaceWire-BK models. Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
2/2024 Updated Design PCIeBPMCX1 Has been updated. The bridge in use since 2007 went EOL and has been replaced with a Pericom PI7C9X130DNDE. The new bridge retains the 1-4 lane PCIe capability and provides the same options for 32/64 bits and 25-133 MHz. Please see the updated manual for settings and more detailed descriptions. In addition the 5V and 3.3V power supplies have been updated to provide up to 15A each. A new feature is an optional AP power connector with a standard 2x3 configuration to match PC internal power harnesses. The rear IO and bezel IO configurations are retained to provide a constant interface for cabling. The bridge is transparent and no SW changes required unless optimizing for high speed DMA operation. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
8/2023 Updated Design VPX-GLIB Has been updated to incorporate the PCIe interface to operate in parallel with the original SPI control path. VPX-GLIB is a multi-purpose hardware design supplying many system supervisor and space saving interfaces. VPX-GLIB is controlled via SPI bus [LVDS] using CLK, EN, SEL [2-0], MOSI, MISO. The SPI interface with the CPU is received and decoded. SPI accesses to internal functions are re-routed to a second decoder which extracts data to be written or packages data to be read. The extracted data is stored into a local register, and then parallel loaded to the target register. Accesses for SMB are re-routed to that interface. The PCie interface operates in parallel with the SPI interface - both affect the same register set allowing for either or both buses to be used for control. Base design provides LVDS, 485, single ended electrical interfaces with conversion, direction and termination control. Local voltage plus external voltage measurements with 3x LM81s, remote temperature measurement [TMP422] with automated HW interface, Multi-voltage inputs with programmable set-points. 10 MHz Clock reference testing and forwarding. Industrial Temperature range. Please see the Dynamic Data Sheet for links to HW manuals and detailed information. Win10 software package available to support access over the PCIe bus.
8/2023 New Design PCIe8LXMCX2HL A customized version of PCIe8LXMCX2. The rear IO options are optimized for the client requirement with the XMC rear IO broken out to 4 connectors per position. The interconnects are a combination of 50 ohm single ended and 150 ohm differential pairs. The differential signals are matched length. Base features common with PCIe8LXMCX2: Adapt 1 or 2 XMCs into a PCIe system. Gen1-3 compatible, Updated switch, clock distribution, incorporated Connector Bus, and power supplies. 8 lane connection to the PCIe bus with 8 PCIe lanes to each of the XMC positions. Options for FANs, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface.
8/2023 Updated Windows Package PCIeAlteraCycloneIV is now supported with Win10/11 drivers and reference SW. Driver and Hardware Manuals are available for download. Both drivers [Linux and Windows] are available to clients of PCIeAlteraCycloneIV along with reference software showing how to use the software to control the User design. Support package includes generic Read and Write operations to support user changes to the base memory map.
PCIeAlteraCycloneIV features Cyclone IV FPGA - 115, GPIO control bus plus 16 DMA channels to support user designs based on RS-485 and / or LVDS IO types. A Spartan 6 FPGA handles the traffic in and out of the PCIe bus and the user has access to the Cyclone IV. 40 differential pairs and 12 TTL IO are available to the user along with 24 PLLs.
07/2023 Updated ASCB interface for PCIe. Due to parts shortages ASCB has been redesigned to provide greater availability. ASCB is supported with two dual redundant ports utilizing the standard DB9 connector and pinout. D [Manchester] and Enhanced [8b10b] protocols supported. Dual Port RAM is used to store messages to transmit and data received from the ASCB interface. DMA is supported. In addition, a PMC position is supplied to support applications with need of local processing in the form of a PrPMC. Alternatively the PMC position can be used to add more IO to your system. Windows® SW package by Dynamic Engineering. Linux package by The Goebel Company.
06/2023 New SpaceWire Monitor Windows® SW package by Dynamic Engineering. SpaceWire Monitor can be used to capture the communication between two SpaceWire nodes. Both sides are captured, filtered and stored to memory. Data is stored by packet and each packet is pre-pended with time, number and size. SpaceWire-Monitor can capture the data needed to do system / platform validation, debug tricky communications issues, capture HW data errors and more. Software currently executes with Linux and Windows®. SpaceWire-Monitor is a build option for PCI, PCIe, PMC, PC104p, and PCI-104 models of SpaceWire IO. All models offered have 576 KBytes of storage per port. DMA transfers data to the user specified file. NVMe or HDD with cache recommended for file storage. Data is stored as binary. Application includes binary conversion utility to provide human readable files. Click below for the SpaceWire-Monitor data page. Use the manuals tab to navigate to the user manual for more detail.
4/2023 Linux Support Package for PMC-Parallel-485-NG1.
PMC-Parallel-485-NG1 provides register based GPIO plus 2 cascaded counters, fused 3.3V, received and redriven differential pair. The counters can be operated with a divided clock with external and internal sources. The counters can be used as interrupt generators. Total count or specific bits within the count can be selected. The base design has 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Linux package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485-NG1. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab. Windows and Linux currently supported.
2/2023 Win 10/11 Driver IP-1553 now features a Window® support package. The hardware includes a Spartan VI FPGA and HOLT 1553 interface. These updates provide Mil-STD-1553 support in an IndustryPack format. Industrial temperature components throughout. SW compatible with the previous versions. Win10 and Linux SW packages. Control all aspects of the single (-1) or two port (-2) models. Each port is dual redundant with header options for direct and transformer coupled operation. IP-1553 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
1/2023 Maxwell-2 Revision 02 released.
Maxwell-2 is a standalone micro computer with FPGA, Memory, CPU and IO. Spartan 6 [45 or 75] with QSPI FLASH to configure. Micro Blaze CPU built into the FPGA fabric allowing embedded Linux applications to run along with custom VHDL/Verilog implementations for your project. DDR, FRAM, FLASH, Ethernet, USB, Parallel Ports, LEDs, RTC with battery back-up, plus push button and dipswitches for user input. Internal power supplies only require a 5V external input. Multiple clock references supplied to FPGA and IO devices. Industrial Temperature components. Reference manual available on the Dynamic Data Sheet. See the Models tab.
12/2022 Win10/11 Support Package for PMC-Parallel-485-NG1.
PMC-Parallel-485-NG1 provides register based GPIO plus 2 cascaded counters, fused 3.3V, received and redriven differential pair. The counters can be operated with a divided clock with external and internal sources. The counters can be used as interrupt generators. Total count or specific bits within the count can be selected. The base design has 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485-NG1. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab. Linux for this model is scheduled.
08/2022 Win10 Support Package for PMC-Parallel-485.
Register based GPIO with options for bezel and rear panel IO. 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
11/22 Updated Design: PCIe8LXMCX2 Adapt 1 or 2 XMCs into a PCIe system with PCIe8LXMCX2. Now Gen1-3 compatible, Updated switch, clock distribution, incorporated Connector Bus, and power supplies. 8 lane connection to the PCIe bus with 8 PCIe lanes to each of the XMC positions. Connector Bus option creates a high speed inter-connect between the XMC rear IO connectors to support Signal Processing and other high bandwidth requirements. Isolation resistors are incorporated for almost zero stub length. Matched length for each option, impedance controlled, differential routing. Standard differential pair definitions. Options for Jn4, Jn6, FANs, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. A detailed selection map is available in the manual. See Dynamic Data Sheet for more information and manuals.
11/2022 New Version IP-Parallel-TTL-PATT features a 32 bit Pattern Generator plus 16 bit GPIO port [TTL / LVTTL interface]. 100 MHz reference along with user programmed divisors to supply COS and Pattern Generation references. Pattern Generator currently has 8 Types to choose from. The first option is User Data. Patterns written to the FIFO [4Kx32] are broadcast at the programmed rate. The remaining types utilize the built in controller to output the selected pattern. The limits [Start and Stop], Rate of Change [Slope], Number of cycles to output [Count], and Horizontal Count [HCount] are used to control the operation of Rising and Falling Ramps, Pyramids and inverted Pyramids, Square Wave, Shift Up, and Trapezoidal waveforms. Various status and optional interrupts are available to manage the interface. The recieve mode can be enabled to operate separately or in parallerl with the Pattern Generator. Data is captured on the rising edge of the reference clock and stored into the Rx FIFO [4Kx32]. Driver has Read and Write File operations for burst reads and writes when using the FIFOs.
In addition, a 16 bit GPIO parallel port with COS [change of state] capability is provided. Selectable Rising, Falling, Interrupt Enable, Polariity, Direction, Edge/Level controls to provide complete control over the interface. Win10/11 support. .
10/2022 New Version IP-Parallel-TTL-DPR provides a parallel interface to interconnect with a memory based system. A19-0, D15-0, READ, WRITE, ACK, BUSY supported. 100 MHz reference used to have precise timing. Simple structure to send commands to the interface to Write to memory, Read from memory and Read multiple from memory. Commands stored in 255 deep FIFO queue. 1Kx16 FIFO to store data from Read commands. In addition, an 8 bit GPIO parallel port with COS [change of state] capability is provided. Programmable sample rate for COS operation. Win10/11 support. Target simulator developed for test purposes. If your timing is different let us know know and we can modify to suit your requirements..
09/2022 Updated Model "ORN1" of ccPMC-BiSerial-VI.
2 ports with SDLC and 2 ports with NRZ/NRZL functions. Parallel port with mux control to select SDLC, NRZ/NRZL, or Parallel port operation. SDLC is Dual Port RAM based with programmable message length, interrupts etc. NRZ/NRZL is highly configurable with number of bits per transfer [packet descriptors], MSB/LSB first operation, Clock Sense, Data Sense, frequency of transmission, time between packets sent, time to wait for end of message, Programmable flags for Almost Full and Almost Empty FIFO. Interrupt or polled operation. 32 differential IO [485 or LVDS]. Temperature Sensor with state-machine to manage serial interface. PLL for custom frequencies. Industrial Temperature components. Rear IO (Pn4). Windows package supports all modes and comes with reference SW and test menu. VxWorks package - 6.9 supported. Linux package released. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
09/2022 Win10 Support Package for PMC-Parallel-485.
New Feature included in support package. Two new utilities are available on the UserAp menu: Print Registers and Modify Registers. Print Registers reads and prints the current contents of the registers within PMC-Parallel-485. Registers supported with structures have the settings displayed showing the current values of the structure. Modify Registers allows the user to change the settings on the board without writing software. Quick start options to program to transmit or receive. Toggle option to have a register change between two values via single key stroke. Great for initial familiarization and to use PMC-Parallel-485 as a tool to interact with other hardware. The rest of the files within UserAp provide a great references for initialization - connecting with the driver, performing IO tests, using interrupts, and more.
PMC-Parallel-485 provides register based GPIO with options for bezel and rear panel IO. 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
08/2022 Win10 Support Package for PMC-Parallel-485.
Register based GPIO with options for bezel and rear panel IO. 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
08/2022 New Model "ORN1" of ccPMC-BiSerial-VI.
2 ports with SDLC and 2 ports with NRZ/NRZL functions. Parallel port with mux control to select SDLC, NRZ/NRZL, or Parallel port operation. SDLC is Dual Port RAM based with programmable message length, interrupts etc. NRZ/NRZL is highly configurable with number of bits per transfer [packet descriptors], MSB/LSB first operation, Clock Sense, Data Sense, frequency of transmission, time between packets sent, time to wait for end of message, Programmable flags for Almost Full and Almost Empty FIFO. Interrupt or polled operation. 32 differential IO [485 or LVDS]. Temperature Sensor with state-machine to manage serial interface. PLL for custom frequencies. Industrial Temperature components. Rear IO (Pn4). Windows package supports all modes and comes with reference SW and test menu. VxWorks is released - 6.9 supported. Linux in process. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
5/2022 New Version: PCIe4LHOTLinkx5-SMB HOTLink is used in applications demanding high speed and high reliability including photography, sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. PCIe4LHOTLinkx5 is a PCI Express device. The -SMB version has a single channel with Tx and Rx ports utilizing the SMB connectors. The HOTLink ports are supported with separate DMA transfer engines plus local memory. Full duplex operation with 256Kbytes of FIFO memory per port. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames. Win10 driver and reference application available. See Dynamic Data Sheet for more information and manuals.
05/2022 PMC-OctalUART-232 Win10 - Dynamic Engineering has updated the software package for PMC-OctalUART-232 with Windows 10 support. The SW package is included with your purchase of PMC-OctalUART-232. Drivers and UserAp reference package with examples for set-up [baud rate, word size, stop bits, RTS/CTS etc.], Transmitting and Receiving characters. Internal and External loop-back examples. External tests with and without flow control in use. Driver includes IOCTLs for write multiple and read multiple. Signals [RX, TX, RTS, CTS, DTR, DSR per port]. Eight ports per device. ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Rear IO model shown below.
04/2022 IP-QuadUART-485 Win10 - Dynamic Engineering has updated the software package for IP-QuadUART-485 with Windows 10 support. The SW package is included with your purchase of IP-QuadUART-485. Drivers and UserAp reference package with examples for set-up [baud rate, word size, stop bits, RTS/CTS etc.], Selection of Full or half duplex RS-485 operation, Transmitting and Receiving characters. Internal and External loop-back examples. External tests with and without flow control in use. Driver includes IOCTLs for write multiple and read multiple. 485 signals [RX, TX, RTS, CTS, DTR, DSR per port]. Four ports per device. Designed to work with Dynamic Engineering IP Carrier group driver package. ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
04/2022 IP-QuadUART Win10 - Dynamic Engineering has updated the software package for IP-QuadUART with Windows 10 support. The SW package is included with your purchase of IP-QuadUART. Drivers and UserAp reference package with examples for set-up [baud rate, word size, stop bits, RTS/CTS etc.], Selection of RS-232 or RS-485 operation, Transmitting and Receiving characters. Internal and External loop-back examples. External tests with and without flow control in use. Driver includes IOCTLs for write multiple and read multiple. 485 signals [RX, TX, RTS, CTS per port] 232 signals[Rx, Tx, RTS, CTS, DTR, DSR, RI, CD per port]. Four ports per device. Designed to work with Dynamic Engineering IP Carrier group driver package. ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
04/2022 PC104p-SpaceWire updated - Dynamic Engineering has updated PC104p-SpaceWire to support the BK and SpaceWire Monitor models. Purchase includes Win10 and Linux SW support. 4 ports each separately programmable to operate up to 200 MHz. DMA engine for each port / direction [8 total]. Time code included. Standard MDM connectors. RMAP with separate Linux package. Industrial temperature components standard. Options for added memory [see -128 models], ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
03/2022 VPX2IP updated - Dynamic Engineering has updated VPX2IP to have Win10 support along with more clocking options and VHDCI connectors at the bezel / front panel. VPX2IP is a 3U 4HP mechanical configuration with two IP Module locations. Front Panel IO is standard utilizing two 68 position VHDCI connectors at the VPX bezel. Compatible with standard VHDCI cable. VHDCIterm68 can be used as a breakout. Rear Panel IO is also available with IP module IO routed to the VPX rear connector [P2/J2]. Multi-word transfers are supported: 64, 32, 16, and 8 bit transfers are easy to implement with standard CPUs. VPX2IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range components, Independent 8 and 32 MHz IP Module operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. PCIe single lane operation. Windows, Linux, and VxWorks drivers and reference software. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
12/2021 Option for alternate pinout of PMC-BiSerial-VI-UART.
The -LM12 option selects an alternate FLASH installation with pinouts matching the Abaco / Radstone PMC-Q1F design. PMC-BiSerial-VI-UART-LM12 features the same design just rearranged. The extra features from the standard -UART design are pushed onto unused pins. 8 UART I/O ports each consisting of RS-485 transmit and receive data. [LVDS is an ordering option] The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the port reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Alternate reference frequencies are available. Reference clock for each port is selectable between the 32 MHz reference and a user programmed PLL frequency. Each UART port has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFOs. DMA support on all channels. 5 modes can be selected per fully independent node: Standard UART (unpacked), Packed, Packetized, Alternate Packetized, and Test. Options for Bezel and Rear IO.
Windows and Linux packages support all modes and comes with reference SW. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
12/2021 Updated SpaceWire Software Release Dynamic Engineering has released revision 1p5 of the Windows 10 support package for SpaceWire-BK models. All types including curent releases of PMC, PCI, PCI-104, PCIe can use the updated package.
PCIe-SpaceWire-BK as well as the other models implement SpaceWire [ECSS-E-ST-50-12C specification] in a convenient format. Four fully independent and highly programmable SpaceWire ports are provided by the SpaceWire-BK design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Rx ports autobaud. First character synchronization. The Win10 software package supports all of the features of the SpaceWire-BK design, and the UserAp reference software demonstrates the features including: internal and external loop-back with and without DMA operation. For example, several frequency files are provided and the UserAp software can automatically load them for you. Set any port to any programmable frequency. The Win10 package is included with your purchase of SpaceWire-BK models. Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package.
11/2021 New Design cPCIBPMC3U32.
3U 4HP cPCI adapter for PMC. Transparent bridged model with 5V / 3.3V compatible PCI interface on primary side and selctable voltage on secondary [PMC] side of bridge. 32 bit plug and play PCI operation. 33/66 MHz primary. Up to the primary frequency for secondary clock. PMC IO through the bezel. Option for rear IO using Pn4/Jn4 routed to cPCI J2. Matched length, impedance controlled [100 ohm differential] for rear IO. Local filtering on 3.3V and 5V power rails with full current mini-planes to power the PMC. +/- 12V also supplied with 1A+ traces. Industrial temperature. Fan option. ROHS option. Conformal Coating option. Isolate by voltage or clock rate. PCI trace lengths are within specification. Reference manual available on the Dynamic Data Sheet. See the Manuals tab.
11/2021 New Design GPIO model of ccPMC-BiSerial-VI.
32 differential IO [485 or LVDS]. Each IO is independent with programming options for Edge or Level, COS (Change of State), Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Rear IO (Pn4). Windows package supports all modes and comes with reference SW and test menu. Linux scheduled. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
10/2021 New Design cPCI3U32B1LPCIeX4. Converts the PCI bus used in cPCI to PCIe to allow use of PCIe modules in a cPCI system. 3.3V and 5V tolerant PCI bus with reverse bridge to create 1 lane PCIe interface. 4 lane connector provided to allow for multiple cable and interface options on the PCIe side. Local high stability 100 MHz generation with shunt to select Spread [SSC] or fixed clock [NSSC] operation. Industrial Temperature components. Support for 4 GPIO, EEPROM, External 12V for designs requiring additional current. 3U 4HP implementation. Transparent bridge does not require programming.
10/2021 Updated Design Parallel-TTL-GPIO Win10 Package. Available in XMC and PMC formats. 64 single ended IO with software programmable voltage reference [3.3V or 5V]. Each IO is independent with programming options for Edge or Level, COS, Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Bezel IO with VHDCI connector and / or Rear IO from (PMC)Pn4, (XMC) Pn4 and/or Pn6
Win10 & Linux support packages. Driver and reference software set [UserAp]. See models tab for manual download - HW and SW.
10/2021 Windows 10 package for UART model of PMC-BiSerial-VI.
8 UART I/O ports each consisting of RS-485 transmit and receive data. [LVDS is an ordering option] The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the port reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Alternate reference frequencies are available. Reference clock for each port is selectable between the 32 MHz reference and a user programmed PLL frequency. Each UART port has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFOs. DMA support on all channels. 5 modes can be selected per fully independent node: Standard UART (unpacked), Packed, Packetized, Alternate Packetized, and Test. Options for Bezel and Rear IO.
Windows package supports all modes and comes with reference SW and test menu. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
09/2021 Updated Linux package for UART model of PMC-BiSerial-VI.
8 UART I/O ports each consisting of RS-485 transmit and receive data. [LVDS is an ordering option] The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the port reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Alternate reference frequencies are available. Reference clock for each port is selectable between the 32 MHz reference and a user programmed PLL frequency. Each UART port has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFOs. DMA support on all channels. 5 modes can be selected per fully independent node: Standard UART (unpacked), Packed, Packetized, Alternate Packetized, and Test. Options for Bezel and Rear IO.
Linux package supports all modes and comes with reference SW and test menu. Compatible with current kernels.
09/2021 Updated RTN10 model of PCI-ECL-II.
Custom Parallel interface. 8 bit parallel data path [NECL input and output] with reference clock and enable. Data valid on programmable edge of clock, enable active high. Programable use of enable. DMA support, 12 bits uncommitted TTL IO. Updated with higher performance memory operation, increased FIFO size, added status, and operational enhancements. Improved DMA performance and new Linux driver with this release.
07/2021 New SpaceWire Monitor package by Dynamic Engineering. SpaceWire Monitor can be used to capture the communication between two SpaceWire nodes. Both sides are captured, filtered and stored to memory. Data is stored by packet and each packet is pre-pended with time, number and size. SpaceWire-Monitor can capture the data needed to do system / platform validation, debug tricky communications issues, capture HW data errors and more. Software is written in C and currently executes on Linux. The Monitor package is designed to utilize the latest Linux SpaceWire release [1.1.4]. SpaceWire-Monitor is a build option for PCI, PCIe, PMC, PC104p, and PCI-104 models of SpaceWire IO. All models offered have 576 KBytes of storage per port. DMA transfers data to the user specified file. NVMe or HDD with cache recommended for file storage. Data is stored as binary. Application includes binary conversion utility to provide human readable files. Click below for the SpaceWire-Monitor data page. Use the manuals tab to navigate to the user manual for more detail.
7/2021 Updated Design Parallel-TTL-GPIO Linux Package. Available in XMC and PMC formats. 64 single ended IO with software programmable voltage reference [3.3V or 5V]. Each IO is independent with programming options for Edge or Level, COS, Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Bezel IO with VHDCI connector and / or Rear IO from (PMC)Pn4, (XMC) Pn4 and/or Pn6
Win10 & Linux support packages. Driver and reference software set [UserAp]. See models tab for manual download - HW and SW.
06/2021 New RMAP SpaceWire Linux software package by Dynamic Engineering. SpaceWire Remote Memory Access Protocol (RMAP) was developed to support reading and writing from/to memory in a remote SpaceWire.node. RMAP can be used to configure a SpaceWire network, control SpaceWire nodes, and transfer data between nodes. Software is written in C and currently executes on Linux. The RMAP package is designed to utilize the latest Linux SpaceWire release [1.1.4] and can be modified to work with other third party SW packages and other companies HW. Click below for the SpaceWire summary page. Use the manuals tab to navigate to the user manual for more detail.
06/2021 Updated SpaceWire Linux Driver and Reference SW by Dynamic Engineering. The new release features enhanced interrupt processing for multi-port DMA operation and modifications to support the RMAP Linux package. The driver has been validated on the P2020 platform (multi-core PPC) which is big endian and i7 for little endian operation. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Win10 and VxWorks also available.
6/2021 Solar Power Dynamic Engineering is pleased to announce that we have added approximately 54 KW of solar power generation to our location. With the addition of the solar panels Dynamic Engineering will be better than net 0 on an annual basis. Dynamic Engineering contracted with Just Leaks for the installation of the system. 133 panels with almost 3000 square feet of collection. Dual sided panels to take advantage of the reflected energy on a commercial reflective roof. Special rack mounts with hinges to allow for future maintenance on the roof without removing the panels. Three phase power generation to allow future connection with storage devices to support our Manufacturing and Engineering requirements.
5/2021 Updated Design: PCIe8LXMCX1 Adapt an XMC into a PCIe system with PCIe8LXMCX1. 8 PCIe lanes routed to the XMC. Matched length controlled impedance traces suitable for Gen1-3. Options for FANs, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Updated with more current on the 5V and 3.3V supplies - with Rev 06 increased to 15A. Industrial Temperature components throughout. Power supplies allow user selection of delayed, immediate, and disabled for the +5V and +3.3V internal power supplies. If your XMC does not use one of the rails your inrush requirement can be reduced by disabling the unused supply. If your system has slow to program devices you will want the immediate turn on setting, and if your device is faster to load you can space out the inrush of the local supplies with the delayed setting. See Dynamic Data Sheet for more information and manuals.
3/2021 New Design cPCIBXMC3U32. Use your XMC in a cPCI environment. 3U 4HP adapter / carrier/ transition from cPCI to XMC standards. cPCIBXMC3U32 incorporates a 32 bit PCI interface [66 MHz capable, universal voltage] and converts to a single lane PCIe interface for the installed XMC device. The bridge is transparent - no SW development to use the adapter. XMC bezel aligns with cPCI bezel. XMC rear IO available with PMC style, XMC style or both connectors via cPCI J2. Industrial Temperature components. More information user manual available on Dynamic Data Sheet.
3/2021 Updated Designs PCI3IP, and PCI5IP - Added Features including VPWR plus upgraded to Spartan VI. PCI3IP features 3 IndustryPack Module positions in a half length PCI format design [Rev 11 and later]. PCI5IP incorporates 5 IP locations in a full length PCI format design [Rev 08 and later]. Both utilize industrial temperature devices. PCI3IP has been in production since 1999. PCI5IP since 2002. Through Dynamic Engineering´s continuous improvement plan the devices are still in production and serving our clients. If your system is PCI limited try the PCIe3IP and PCIe5IP models with similar features.
VPWR is the new name for the 5V rail supplied to the installed IndustryPack modules. 5V is the default to accomodate current designs. When the pin known as Reserved 1 [Pin 36] is grounded by one or more of the installed IP modules VPWR is switched to 3.3V as well as the reference to the terminations. Current FPGAs generally are not 5V tolerant plus require 3.3V for operation. The use of VPWR can save level translators and regulators on the IP Module.
Both of the updated designs are compatible with the unified DynEngIpCarrier driver, and DynEngIpCarrierAp. Driver and hardware support auto loading of IP Module drivers, access to each IP control register [carrier FPGA to control clock rate, interrupts, byte swapping, bus error, 32 bit conversion control etc.], Carrier registers for switch, revision, LEDs, interrupt status, etc. Full access to each of the IP address spaces [ID, IO, INT, MEM]. Reference Application provides examples of communicating with an IP in all address spaces, plus interrupts and handling bus errors. The reference SW for the carrier uses IP-Test as the target [modified IP-Parallel-HV]. IP Modules with Win10 driver packages have support specific to that module. Supported modules are auto-loaded. When an IP without a support package is detected IP-Generic is installed allowing use of third party IPs with the DynEngIpCarrier driver on a Dynamic Engineering IP Carrier.
3/2021 Updated Driver and Reference SW IP-Parallel-IO Win10 SoftWare package. The 7 standard models of IP-Parallel-IO [-TTL, -1, -2, -3, -4, -5, -485] are now supported with a unified Windows 10 reference software package. With this release all 7 models are covered. Revision 03 and 04 PCBs are compatible [Spartan II and Spartan 6 based designs]. The new unified driver package is compatible with the DynEngIpCarrier driver package. The new unified IpParIoUserAp has routines to demonstrate the use of the two counter timers, configuring and using the IO. Use of interrupts to manage the received IO and counter timers is included. Programming of the output waverform option is also included. The reference menu auto detects the type of IP installed and displays along with the details of that model. Carrier frequency of operation selection is demonstrated in the ATP Menu Item. The IOCTLs are grouped by _IO_ for common calls that apply to all 7 models, _N_ for calls specific to a particular model. The IOCTL is the same in all cases. The driver uses a common structure to communicate with the User program and auto alligns to the installed HW. A great reference to get you started. Included with your purchase of the IP-Parallel-IO family. HW and SW manuals available on the Dynamic Data Sheet - See link above or click on the photo.
2/2021 New Design Parallel-TTL-GPIO. Available in XMC and PMC formats. 64 single ended IO with software programmable voltage reference [3.3V or 5V]. Each IO is independent with programming options for Edge or Level, COS, Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Bezel IO with VHDCI connector and / or Rear IO from (PMC)Pn4, (XMC) Pn4 and/or Pn6
Win10 support with Driver and reference software set [UserAp]. See models tab for manual download - HW and SW. Linux in development.
1/2021 Updated Design PMC-BiSerial-VI-HW1 is the ported and upgraded version of PMC-BiSerial-III-HW1. The updated version incorporates a Spartan VI FPGA, and industrial temperature components. These updates will allow for continued operation for years to come. SW compatible with the previous versions. Win10 and Linux SW packages. Linux available, Win10 in process. PMC-BiSerial-VI has 34 independent differential IO. Each of the IO have programmable termination, and direction controls. The IO is available for system connection through the front panel SCSI connector and / or Pn4. SCSI Cable and HDEterm68 can be used as a breakout for the IO.
The HW1 protocol implemented provides 32 Manchester encoded data ports per PMC-BiSerial-VI. Each port can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 channels. The 32 port plus 2 additional IO can be used for a parallel port. Bit level programmable for function, Direction, Termination. Option to use I2O or standard interrupts. The reference frequencies can be derived from the on-board oscillator or SW programmable PLL. The pin definitions are consistent with the PMC-BiSerial-III-HW1 design to allow migration to the PMC-BiSerial-VI-HW1 quickly and easily.
1/2021 Updated Driver and Reference SW For use with IP-HaveQuick- Win10 SoftWare package. IP-HaveQuick supports both Transmission and Reception of HaveQuick data. HaveQuick is a Time of Day interface. The 1PPS sync pulse is followed by manchester encoded data with the data and time. New with this release is a control bit that allows the user to select standard [Msb] and Lsb First operation. The ones, and synchronization pattern are not affected by the selection. The payload data and parity are reversed on a byte basis when selected. The Win10 package includes demonstrations of setting up the transmitter with the current data and time as well as receiving data via register reads or using the FIFO storage. Interrupt and polled operation supported and demonstrated. The new driver package is compatible with the DynEngIpCarrier driver package. A great reference to get you started. Included with your purchase of IP-PAR-HQT
1/2021 Facilities Improvement Dynamic Engineering has contracted to add approximately 54 KW of solar power to our electrical system. 3 phase system using 133 panels. Expected to be on-line in time for summer. The roof was recently redone to improve drainage and insulation value with a highly reflective surface. The Bifacial panels use the direct energy from the sun plus the reflected energy from the roof to generate electricity.
12/2020 Updated Driver and Reference SW For use with IP-Parallel-IO- Win10 SoftWare package. An integration effort is underway with the 7 standard models of IP-Parallel-IO [-TTL, -1, -2, -3, -4, -5, -485] to create a unified Win10 driver package. With this release the TTL and 485 models are covered. Revision 03 and 04 PCBs are compatible [Spartan II and Spartan 6 based designs]. The new unified driver package is compatible with the DynEngIpCarrier driver package. The new unified IpParIoUserAp has routines to demonstrate the use of the two counter timers, configuring and using the IO. Use of interrupts to manage the received IO and counter timers is included. The reference menu auto detects the type of IP installed. Frequency switching is demonstrated in the ATP option. The IOCTLs are grouped by _IO_ for common calls that apply to all 7 models, _485_ for calls specific to the -485 and _TTL_ for the TTL specific calls. A great reference to get you started. Included with your purchase of the IP-Parallel-IO family
10/2020 Updated Driver and Reference SW For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP - Win10 SoftWare package. An integration effort is underway with the 4 models [PCI5IP, PCI3IP, PCIe5IP, PCIe3IP] now covered by the unified DynEngIpCarrier driver, and DynEngIpCarrierAp. cPCI and PC104p models will be added. Driver supports auto loading of IP Module drivers, access to each IP control register [in carrier FPGA to control clock rate, interrupts, byte swapping, bus error, 32 bit conversion control etc.], Carrier registers for switch, revision, LEDs, interrupt status, etc. Full access to each of the IP address spaces [ID, IO, INT, MEM]. Reference Application provides examples of communicating with an IP in all address spaces, plus interrupts and handling bus errors. The reference SW for the carrier uses IP-Test as the target [modified IP-Parallel-HV]. IP Modules with Win10 driver packages have support specific to that module. Supported modules are auto-loaded. When an IP without a support package is detected IP-Generic is installed allowing use of third party IPs with the DynEngIpCarrier driver on a Dynamic Engineering IP Carrier.
7/2020 New Product Announcement: PCIe-Harpoon
PCIe-Harpoon can be used for simulation, control, command and other embedded IO functions. The
Available now.
6/2020 Linux Driver IP-1553 now features a Linux support package. The hardware includes a Spartan VI FPGA and HOLT 1553 interface. These updates provide Mil-STD-1553 support in an IndustryPack format. Industrial temperature components throughout. SW compatible with the previous versions. Win10 and Linux SW packages. Control all aspects of the single (-1) or two port (-2) models. Each port is dual redundant with header options for direct and transformer coupled operation. IP-1553 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
6/2020 IP-BiSerial-VI-GPIO - New model of IP-BiSerial-VI released. The GPIO model features 24 differential IO configured as a parallel port. Each bit is programmable to be an input or an output. Polarity, Termination, Edge/Level interrupt triggering with separate Rising and Falling edge enables. Interrupt or polled operation. Direct and filtered data ports. User programmable PLL or local oscillator selection for COS reference. 485 and LVDS IO. Windows 10 and Linux support - see Dynamic Engineering IP carriers
[ PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PCI-104, VPX2IP]. Industrial temperature standard.
IP-BiSerial-VI base features include: 24 independent differential IO each with programmable direction and termination. LVDS, RS485, and mixed IO types. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. 8 and 32 MHz IP Module operation. Use this IndustryPack module to implement Manchester, Miller, Serial and Parallel IO, telemetry, communications, command and control etc. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
3/2020 Updated Design PMC-BiSerial-6T20 has been upgraded to incorporate a Spartan VI FPGA, and industrial temperature components. These updates will allow for continued operation for years to come. SW compatible with the previous versions. Win10 SW package. PMC-BiSerial-6T20 has 20 independent transformer coupled IO plus 2 direct connection differential IO. Each of the transformer coupled IO have resistive and capacitive coupling with SW control. The discretes have the resistive termination. The IO is available for system connection through the front panel SCSI connector. SCSI Cable and HDEterm68 can be used as a breakout for the IO. The pin definitions are consistent with the PMC-BiSerial-3T20 design to allow migration to the PMC-BiSerial-6T20 quickly and easily.
3/2020 Updated Design XMC-Parallel-TTL has been upgraded to incorporate a Spartan VI FPGA and VHDCI interface. These updates will allow for continued operation for years to come. Industrial temperature components throughout. SW compatible with the previous versions. Win10 SW package. XMC-Parallel-TTL has 64 independent digital IO. The high density makes efficient use of precious XMC slot resources. The IO is available for system connection both through the front panel and via the rear [Pn4, Pn6] connectors. A high density 68 pin VHDCI front panel connector provides the front panel IO. HDEterm68 can be used as a breakout for the front or rear panel IO. The pin definitions are consistent with the PMC-Parallel-IO design to allow migration to the XMC-Parallel-TTL quickly and easily.
3/2020 New Design IP-Relay16 has been designed to support previous clients of the Systran IP-Relay16 design. 16 Form C relays. The relays are controlled by the host by setting or clearing bits in the Relay Control register. Each bit corresponds to one relay. When set the relay is energized. When cleared the relay is returned to the default state. Back EMF protection is provided on the control side of the relay. The voltage rating on each relay is up to 220 VDC, 250 VAC and 60W or 62.5 VA. The IP IO connector is limited to about 1 A per pin. The traces on the IP are rated for 1.5A. Industrial temperature components throughout. SW compatible with the previous versions. Win10 SW package. IP-Relay16 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
03/2020 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated VxWorks Driver for Versions 6.9 and 7. The driver has been validated on the P2020 platform (multi-core PPC) which is big endian. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 and Linux also available.
2/2020 Updated Design IP-1553 has been upgraded to incorporate a Spartan VI FPGA and HOLT 1553 interface. These updates will allow for Mil-STD-1553 support in an IndustryPack format for years to come. Industrial temperature components throughout. SW compatible with the previous versions. Win10 SW package. Control all aspects of the single (-1) or two port (-2) models. Each port is dual redundant with header options for direct and transformer coupled operation. IP-1553 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
1/2020 Updated Driver package for KAON1 interface released - TTL and HOTLink interfaces with command / response type interaction. 2 Ports per ccPMC-HOTLink-KAON1. A new Win10 driver and reference software package has been developed. Linux also available.
The main purpose is to provide an interface to allow a PC or other computer to communicate directly with KAON1 interface. The KAON1 interface is bidirectional and utilizes both TTL and HOTLink serial interfaces. Each side is supported with large FIFOs. "Channelized DMA"™ on TX and RX. PLL support for custom frequencies. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information.
12/2019 Updated Hardware Release Dynamic Engineering has released an updated model - PCIe-SpaceWire. The PCIe-SpaceWire internal PCI bus now operates at 50 MHz for a 50% gain in bandwidth. The increase in BW means more ports can operate at higher frequencies with greater loading.
PCIe-SpaceWire implements SpaceWire [ECSS-E-ST-50-12C specification] in a convenient PCIe format. Four fully independent and highly programmable SpaceWire ports are provided by the PCIe-SpaceWire design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. PCIe-SpaceWire provides a bridge from PCIe ⇔ SpaceWire. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
12/2019 IP-BiSerial-VI-BA27 - Update to BA27 model with more programmability. Added features include PDD = Pre Data Delay - a programmable delay from external trigger or SW enable to start transmitting, IWG = Inter Word Gap = a programmable delay between transmitted data, MultiCycle - operation with multiple words transmitted based on FIFO status. SingleCycle mode retained. 16,17,32,34 bit transfers. Msb/Lsb first operation. Programmable frequency. 485 and LVDS IO. Windows 10 and Linux support - see Dynamic Engineering IP carriers
PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PCI-104, VPX2IP]. Industrial temperature standard.
IP-BiSerial-VI base features include: 24 independent differential IO each with programmable direction and termination. LVDS, RS485, and mixed IO types. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. 8 and 32 MHz IP Module operation. Use this IndustryPack module to implement Manchester, Miller, Serial and Parallel IO, telemetry, communications, command and control etc. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
11/2019 Updated Driver package for ARC-210 interface released PCIe-BiSerial-DB37-LM9 supports communications with ARC-210 radios. A new Win10 driver and reference software package has been developed. Linux also available.
The main purpose is to provide an interface to allow a PC or other computer to communicate directly with an ARC-210 radio. The ARC-210 interface is bidirectional and is fully independent for Tx and Rx. Each side is supported with 4Kx32 Data FIFO plus 2Kx32 Packet FIFO. The transmitter "SendTiming" signal can be set to output the reference clock to allow for loop-back and alternate purpose uses. Interrupt or polled operation. "Channelized DMA"™ on TX and RX. 12 bit GPIO port [termination, direction independent on each bit]. RS-485 IO. TX in transmit SendTiming mode supported with PLL for user frequency. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information. This design can be ported to our other BiSerial formats - PMC, PCI-104 etc. Please contact Dynamic Engineering for these options.
11/2019 IP-BiSerial-VI-USR - user configurable / programmable FPGA based IP Module with 24 differential IO. Reference design [VHDL] available. On board FLASH to store the FPGA image for "instant on" operation. Windows and Linux support - see Dynamic Engineering IP carriers [PCI, PCIe, cPCI, PCI-104, VPX]. Industrial temperature standard. Spartan 6 LX25 device with block RAM and clocking elements to complete your design.
24 independent differential IO each with programmable direction and termination. LVDS, RS485, and mixed IO types. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. 8 and 32 MHz IP Module operation. Use this IndustryPack module to implement Manchester, Miller, Serial and Parallel IO, telemetry, communications, command and control etc. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Check the non-USR list - we may have your interface already imlemented.
9/2019 PMC2mPCI released PMC2mPCI is an adpater to convert between mPCI type III and PMC. It is a passive design with no additional SW required. Matched length, impedance controlled PCI bus with filtering. Mounts to any standard PMC location. Comes with mounting hardware. mini-PCI type III cards can add wireless and other interfaces to your PMC based project.
9/2019 Renewed Product Dynamic Engineering now has SCSI Cable. After being frustrated trying to find proper cables to support our clients we have decided to make SCSI cables a stocked item. 3Ft, 6Ft, 9Ft lengths with Latch -Block [clip] and Thumbscrew [screw] terminations available. Suitable for operation with PMC-BiSerial-VI and other embedded electronics using the SCSI connector. See HDEterm68 for a SCSI compatible screw terminal breakout.
9/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated VxWorks Driver for Versions 6.9 and 7. The driver has been validated on the P2020 platform (multi-core PPC) which is big endian. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 and Linux also available.
8/2019 PMC-BiSerial-VI-OSEH released PMC-BiSerial-VI-OSEH is an updated version of the original PMC-BiSerial-III-OSEH design. PMC-BiSerial-VI-OSEH is supported with a Win10 driver and reference software. Linux and VxWorks available by special request. OSEH is a 32 bit serial transfer with a gated clock reference. Data is transmitted until the local FIFO is empty. The design supports internal and external Tx clock references. The internal rate is set by the PLL - SW controlled. Programmable transmit rate, multiple interrupt options, programmable FIFO level, internal loop-back and more. 132Kx32 FIFO for transmit and receive ports. Independent DMA for Tx and Rx functions. RS485 based with LVDS as an option. The base design comes with bezel IO. Rear [Pn4] IO is an option. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information.
8/2019 Updated SoftWare Release Dynamic Engineering has released Win10 support for the BK models of SpaceWire. Covered are PMC-SpaceWire-BK, PCI-SpaceWire-BK , PCIe-SpaceWire-BK models in the standard, -128 and -128RX configurations. The support package comes with the Win10 signed driver and reference SW. The reference software provides examples of how to use, and how to test the SpaceWire devices including the use of DMA, programming the PLL, transmitting and receiving embedded data or files. A Quick Start User guide is now available with information about the included menu´s and in particular how to send or receive files using the menu. No user SW required.
The Dynamic Engineering SpaceWire family implements SpaceWire [ECSS-E-ST-50-12C specification] in a series of convenient formats. Four fully independent and highly programmable SpaceWire ports are provided. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
8/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated VxWorks Driver for Version 7. The driver has been validated on VxWorks-7 SR0540 SMP on the P2020 platform (multi-core PPC) which is big endian. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 andLinux also available.
8/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated Linux Driver [1.2]. The driver has been validated on an i7 Ubuntu server running 3.8.0-42 kernel (64 bit) SMP, Ubuntu server running 4.18.0-25 kernel (64 bit) SMP, and P2020 (32 micro-controller) running 2.6.35 (32 bit) SMP. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 and VxWorks also available.
7/2019 New SoftWare Release Dynamic Engineering has released Win10 support for the BK models of SpaceWire. Covered are PMC-SpaceWire-BK, PCI-SpaceWire-BK , PCIe-SpaceWire-BK models in the standard, -128 and -128RX configurations. The support package comes with the Win10 signed driver and reference SW. The reference software provides examples of how to use and how to test the SpaceWire devices including the use of DMA, programming the PLL, transmitting and receiving embedded data or files. The Dynamic Engineering SpaceWire family implements SpaceWire [ECSS-E-ST-50-12C specification] in a series of convenient formats. Four fully independent and highly programmable SpaceWire ports are provided. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
7/2019 New HW Release VPX-3U-COOL joins VPX-6U-COOL to provide cooling to VPX 3U hardware. Up to 6 FAN´s mounted per board with options for direction, voltage, location, zero slot or high velocity. Other versions available for cPCI 6U and PC104/PCI-104, and VME 6U
7/2019 New Hardware Release Dynamic Engineering has released a new SpaceWire model - PCIe-SpaceWire. PCIe-SpaceWire implements SpaceWire [ECSS-E-ST-50-12C specification] in a convenient PCIe format. Four fully independent and highly programmable SpaceWire ports are provided by the PCIe-SpaceWire design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. PCIe-SpaceWire provides a bridge from PCIe ⇔ SpaceWire. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
6/2019 New Driver Package Windows 10 for IP-Parallel-IO family now available - TTL model with 48 independent TTL lines, -485 model with 24 differential pairs, and the 5 versions with mixed differential and single ended. Each model has two built in timers, interrupts, synchronization, register based IO. Driver calls are matched with Win7 version to minimize User Application changes when transitioning to Windows 10. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
5/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated Linux Driver [1.1.1]. The driver has been validated on an i7 Ubuntu server running 3.8.0-42 kernel (64 bit) SMP P2020 (32 micro-controller) running 2.6.35 (32 bit) SMP. All 6 models of SpaceWire have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous.
5/2019 Updated Driver and Reference SW Dynamic Engineering IP Carriers and IP-Generic now have Win10 support. The carrier driver works with IP Module drivers to support any installed IP´s. IP-Generic is used with Dynamic Engineering IndustryPack carriers to faciliate use with third party IP Modules. Read, Write, Interrupts, Readfile, Writefile operations are supported along with all IP "Spaces". Support to access and control the adapter to set slot frequency, enable interrupts, check status etc. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP See new releases for IP Module Support. Manuals are available on each of the Carrier pages. Drivers support all DE carrier functions - selecting 8 or 32 MHz per position, reading IDPROM, 32 and 64 bit automatic data width conversion, byte swapping etc.
5/2019 Updated Driver and Reference SW IP-PULSE is now supported with Win10 driver and reference SW. IP-Pulse features four independent pulse generators with TTL, 422, and mixed Output options. Synchronization between generators, phase shifting during operation to simulate acceleration or deceleration, programmable number of pulses output or continuous mode, time asserted, time deasserted, and inverted options. Interrupt per pulse or completion of programmed number of pulses. The driver and reference SW package supports API programming and includes a user interface to program pulse generation. The user interface provides a simple method to use IP-Pulse as a test asset without writing any software. Features like pressing a key to repeat the programmed pulse train are handy when debugging with a scope. All of the basic features contained in the API are supported. Please see the Hardware, Software, and Quick Start guide for the details. Download from the product page.
The IP-Pulse module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
4/2019 New Adapter Use UARTcable8 to convert / adapt PMC-BiSerial-VI-UART to standard DB9 connectors. Up to 8 ports of LVDS, RX-485, RS-422 UART protocol hosted by PMC-BiSerial-VI are converted from a SCSI connector system to DB9 using industry standard pinouts. Available to direct mount or with a chassis [DIN Rails]. ROHS and Non-ROHS, conformal coating options.
4/2019 New Product PC104p-BiSerial-VI
New BiSerial design for PCI-104 / PC104p with Spartan VI FPGA. [75 is the standard size]
16 Differential IO can be RS422, RS-485, LVDS each with separate controls for termination and transmit/receive.
8 TTL IO are provided, each is programmable as an input or output.
4 ADC and 4 DAC are supported. 16 bit devices with high speed serial interface to the FPGA. Discrete locations to allow for filtering and scaling.
PCI clock, Oscillator, external IO, and PLL [4 inputs to FPGA] form the clocking options.
128Kx32 x2 FIFO´s can be added to the PCB for designs with larger storage requirements.
PCI bus supported with DMA and target accesses - 32/33
Industrial Temperature components
Port designs from any of the BiSerial family [IP, PMC, PCIe, PC104p] or send in your specifications for a custom version. BA14 is the first design ported - all 16 of the differential IO are used to create a customized UART interface. See the Dynamic Data Sheet for more information.
4/2019 Updated Driver and Reference SW IP-PULSE is now supported with Win7 driver and reference SW. IP-Pulse features four independent pulse generators with TTL, 422, and mixed Output options. Synchronization between generators, phase shifting during operation to simulate acceleration or deceleration, programmable number of pulses output or continuous mode, time asserted, time deasserted, and inverted options. Interrupt per pulse or completion of programmed number of pulses. The driver and reference SW package supports API programming and includes a user interface to program pulse generation. The user interface provides a simple method to use IP-Pulse as a test asset without writing any software. Features like pressing a key to repeat the programmed pulse train are handy when debugging with a scope. All of the basic features contained in the API are supported. Please see the Hardware, Software, and Quick Start guide for the details. Download from the product page.
The IP-Pulse module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
4/2019 New Product XMC-UNIV-TEST Ever need to access to the component side of an XMC? Now you can - install XMC vertically with the component side exposed. Up to 8 lanes (PCIe) supported. Headers for JTAG, I2C, switch to set Global Addresses, and extra grounds(8). +12V and 3.3V routed with VPWR tied to 12V. Header for -12V. SCSI connector plus header to support Pn6 IO. Compatible with HDEterm68 for breakout or loop-back.
4/2019 Updated Driver Package Linux for Dynamic Engineering IndustryPack Carriers and Modules. Full suite of IndustryPack carriers and expanded module support. IP-Parallel-IO family now supported - -TTL model with 48 independent TTL lines, -485 model with 24 differential pairs, and the 5 versions with mixed differential and single ended. Each model has two built in timers, interrupts, synchronization, register based IO. Other IP models include IP-BiSerial-VI Spartan VI with 24 LVDS or 485 IO - for user specific IO requirements, IP-OptoISO-16 16 Opto coupled IO 1.5A, 60V rated, IP-Parallel-HV 24 0-30V singled ended IO. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
1/2019 Updated Driver and Reference SW IP-1553 is now supported with Win7 driver and reference SW. Control all aspects of the single or two port models. Each port is dual redundant with strapping options for direct and transformer coupled operation. The IP-1553 module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
11/2018 Updated Driver and Reference SW IP-Generic now has updated Win7 driver and reference SW support. IP-Generic is used with Dynamic Engineering IndustryPack carriers to faciliate use with third party IP Modules. Read, Write, Interrupts, Readfile, Writefile operations are supported along with all IP "Spaces" Support to access and control the adapter to set slot frequency, enable interrupts, check status etc. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
10/2018 Updated Driver and Reference SW PMC-BiSerial-III-RL1 now has Win7 driver and reference SW support. Windows 7, 64 and 32 bit reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PMC-BiSerial-III-RL1 along with reference software showing how to use the drivers to control the interface. PMC-BiSerial-III-RL1 provides eight UART I/O channels each consisting of RS-485 transmit and receive data. The UART interface uses a 16x clock to detect received data bits. The interface can operate at up to 10 Mbits/second using a 160 MHz clock. Programmable PLL reference. DMA is supported for each channel independently. Each UART channel has 1K x 32 FIFO for transmit and another 1Kx32 for receive. Please see the hardware manual for the details.
9/2018 Updated Driver and Reference SW PMC-BiSerial-III-HW2 now has Win7 driver and reference SW support. Windows 7, 64 and 32 bit reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PMC-BiSerial-III-HW2 along with reference software showing how to use the drivers to control the interface. PMC-BiSerial-III-HW2 features 8 channels of the HW1 protocol, plus 24 blocks of Asynchronous or SDLC IO. SDLC takes 4 blocks per channel [up to 6 ports] and the Asynchronous takes two [up to 12 ports]. Each HW1 channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 blocks. The SDLC channels are programmable for frequency using the PLL. The Asynchronous channels are designed with a UART style protocol. Please see the hardware manual for the details.
9/2018 New Product PMC-UNIV-TEST Install your PMC vertically with the component side exposed for efficient use of your time. Testpoints on the PCI signals plus JTAG and extra grounds(8). SCSI connector to support Pn4 IO. ENG model has both PMC and Carrier side connectors installed to use in your system - expose PCI signals with the PMC attached to the host. Our engineers and manufacturing manager report this device is a real time saver.
8/2018 Updated Driver and Reference SW PC104p-BiSerial-III-BA14 now has Win7 driver and reference SW support. Windows 7 and Win32 reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PC104p-BiSerial-III-BA14 along with reference software showing how to use the drivers to control the interface. PC104p-BiSerial-III-BA14 features DMA operation to support a specialized serial port. 8 copies of the transmit signals. 8 inputs with software selecting which port to utilize. Status and programmable interrupts for polled or interrupt driven operation. Serial data is similar to UART but MSB first, 16/17 bits long. RS485 IO. Option for LVDS.
7/2018 Updated Engineering Kit and Hardware PCIeAlteraCycloneIV is now supplied with an updated FLASH. The Engineering Kit has been updated to compile in Quartus 17.1 [free download from Intel] and incorporate the new SFL [Serial Flash Loader] required for the new Intel FLASH device. Use our reference design as a starting point for your design. Pinouts, FLASH definition etc. are set-up and ready to use. Designed to be easy to remove our IO control and add yours. User Configurable Logic - PCIe Altera Cyclone IV 485/LVDS comes with everything you need to load your Altera program into the Cyclone IV. Fantastic for development, simulation, special purpose interfaces, multiple serial and / or parallel channels. FLASH and on-the-fly reloading for configurable and reconfigurable logic implementations.
Windows 7 and Linux reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PCIeAlteraCycloneIV along with reference software showing how to use the drivers to control the User design. PCIeAlteraCycloneIV features Cyclone IV FPGA - 115, GPIO control bus plus 16 DMA channels to support user designs based on RS-485 or LVDS IO types. A Spartan 6 FPGA handles the traffic in and out of the PCIe bus and the user has access to the Cyclone IV FPGA for their IO driven design. 40 differential pairs and 12 TTL IO are available to the user along with 24 PLL´s.
7/2018 PMC-BiSerial-VI-S311 released PMC-BiSerial-VI-S311 is an updated version of the original PMC-BiSerial-S311 design with an added 2nd port and new features. PMC-BiSerial-VI-S311 is supported with a Win7 driver and reference software. Linux and VxWorks available by special request. The updated design has 2 ports configured to interact with the S311 bus (Northrop Grumman RADAR). Each port is independent with programmable transmit rate, multiple interrupt options, programmable FIFO level, internal loop-back and more. The ports are RS485 based with LVDS as an option. The base design comes with bezel IO. Rear [Pn4] IO is an option. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information.
6/2018 Updated Support: IP-Parallel-IO is an IndustryPack supporting both Differential [RS-485, RS-422, LVDS] and single ended [LVTTL] IO types. The ordering options include: -TTL with 48 TTL IO, -485 with 24 differential pairs, and -1 through -5 with different combinations of TTL and differential IO. All IP-Parallel-IO models are now supported with Win7 driver and reference applications. IP-Parallel-IO can be adapted to a variety of systems with different IP carriers. PCIe5IP, PCI5IP, cPCI4IP, PC104p4IP are a few examples. See Dynamic Data Sheet for more information plus downloadable Hardware and Software manuals.
6/2017 Win7 driver for IP-QuadUART-485 released. IP-QuadUART-485 provides 4 UART ports each with 128 byte FIFO´s and RS-485 IO. RX, TX, RTS, CTS, DSR, DTR. XR16C854 UART device. Use the new driver and reference software with any Dynamic Engineering IP Carrier - PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP , cPCI4IP, PC104p4IP are a few examples. The reference SW package includes example software using all of the major functions including operation with and without RTS/CTS performing local loop-back routines. Source supplied for reference SW to allow easy modification for your project.
4/2018 PCIe4LBPCI riser card with conversion to support PCI in PCIe position. DMA and interrupts supported. 32/25 ↣ 64/133 operation. Industrial Temperature range. Transparent Bridge. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
4/2018 PMC-OctalUART-232 features 8 (16550 compatible) UART ports with RS-232 signaling. RX, TX, RTS, CTS, DTR, DSR supported on each port. Front and rear IO options. Industrial Temperature range. Industry standard IO definitions and memory map allow PMC-OctalUART-232 to be used in place of PMC-OCTPRO-232. Win7, Linux, VxWorks support. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
3/2018 VPX8LXMC3U is used to mount an XMC into a VPX position. Options for conduction cooled or air cooled environments. REF CLK is supported along with local 100 MHz reference and high speed low jitter devices for Gen1-3 SSC and NSSC operation. Options for PMC, and/or XMC style rear IO connections. Controlled impedance, differentally routed rear IO. Industrial Temperature range. +12, 5, 3.3V, -12V supplied to installed XMC. Selectable VPWR [5V or 12V]. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
2/2018 VPX-GLIB Global Interface Board - VPX-GLIB is a multi-purpose hardware design supplying many system supervisor and space saving interfaces. VPX-GLIB is controlled via SPI bus [LVDS] using CLK, EN, SEL [2-0], MOSI, MISO. Currently the SEL encoding 000, and 001 are used for internal SPI controlled register access with SEL 010 used for conversion to SMB. The SPI interface with the CPU is received and decoded. SPI accesses to internal functions are re-routed to a second decoder which extracts data to be written or packages data to be read. The extracted data is stored into a local register, and then parallel loaded to the target register. Base design provides LVDS, 485, single ended electrical interfaces with conversion, direction and termination control. Local voltage plus external voltage measurements with 3x LM81´s, remote temperature measurement [TMP421] with automated HW interface, Multi-voltage inputs with programmable set-points. 10 MHz Clock reference testing and forwarding. Industrial Temperature range. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
12/2017 IP-BiSerial-VI-BA27 provides a programmable serial interface with transmit and receive full duplex. Data and clock signals, 16, 32 bit lengths plus programmable parity, Msb/Lsb first operation. 4Kx16 FIFO´s for each direction. RS485 standard, LVDS option. programmable operational frequency. Added features: Programmable Done Pulse at end of transmission. Programmable delay from last clock and programmable width of pulse. Software request activated pulse option too. 16 bit Parallel port with programmable direction per bit, and termination per bit. This is an update to the BA13 design and recommended for new projects. Win7 driver and reference software. Based on IP-BiSerial-VI - FPGA based with 24 independent differential IO each with programmable termination. Matched length, impedance controlled routing. Programmable PLL with 4 clock references [not implemented for BA27]. Industrial Temperature range. 8 and 32 MHz IP Module operation. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
11/2017 Win7 driver for IP-Crypto released. IP-Crypto provides an interface to KYK-13 with options for the different voltage standards. In addition the unused [by KYK-13 function] IO are provided as a parallel port with bit wise programming, interrupts etc. Use the new driver and reference software with any Dynamic Engineering IP Carrier - PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI4IP, PC104p4IP are a few examples. The reference SW package include "Read-KYK" and local loop-back routines demonstrating the use of IP-Crypto.
10/2017 Linux For SpaceWire updated Version 1.09 supports the current line-up of K and BK 4 port SpaceWire boards including PMC-SpaceWire, PCI-SpaceWire, PC104p-SpaceWire. The driver and reference application were developed and tested on a Ubuntu server 64 bit server running 3.8.0-42 kernal (64bit) SMP as well as 2.6.35 (32 bit) SMP on a P2020 platform. ENET-SpaceWire uses this driver in our Router/Bridge application. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Available now.
9/2017 PCIe8LSwVPX3U updated PCIe8LSwVPX3U is an 8 lane PCIe adapter with switch isolation for VPX development. The switch isolates the spread spectrum clocking found in most PC´s from the VPX port. User selectable SSC and NSSC clocking on the VPX port. REF CLK supported [25 MHz SSC]. PCIe 3.0 compliant, 1-8 lanes can be used by the installed VPX. Local power conversion for the 3.3V and 5V rails with efficient switching power supplies. Secondary power connector can be installed for high power consumption VPX cards. 10A on 3.3V and 5V rails max. Power monitoring circuits on the VPX and switch power rails. Status indicators for switch. SMA connectors on the spare SSC and NSSC ports. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS. Available now.
8/2017 Added Support: IP-ReflectiveMemory is now supported by a Windows® 7 compatible driver. The driver and reference application "UserAp" are included with purchase of IP-ReflectiveMemory. Hardware features include operation with standard Ethernet cable, option for client cable configuration, rapid update to other nodes - up to 256 total, LVDS IO with DIODE protection, 256Kx16 RAM, ROHS and standard processing, Standard and Extended temperature. Additionally customization is possible within the Xilinx programmable logic.
8/2017 Added Support: PMC Parallel IO is now supported by a Windows® 7 compatible driver. The driver and reference application "UserAp" are included with purchase of PMC-Parallel-IO. Hardware features include 64 open drain TTL connections with options for front and rear IO, ROHS and standard processing, Standard and Extended temperature. Additionally customization is possible within the Altera programmable logic. Available since 1999, PMC-Parallel-IO is a great example of Dynamic Engineering´s commitment to our clients.
8/2017 PMC BiSerial VI UART updated PMC BiSerial UART has been updated to include higher speed operation with the PLL - now up to 4 Mbit operation. The Linux driver is now available too. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. Operational reference programmable on a port by port basis to be 32 MHz or user programmed PLL [up to 64 MHz]. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized plus alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid mode where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® and Linux with VxWorks in development. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
7/2017 Added Support: IP-Parallel-IO is an IndustryPack supporting both Differential [RS-485, RS-422, LVDS] and single ended [LVTTL] IO types. The ordering options include: -TTL with 48 TTL IO, -485 with 24 differential pairs, and -1 through -5 with different combinations of TTL and differential IO. IP-Parallel-TTL and IP-Parallel-4 are now supported with Win7 driver and reference applications. IP-Parallel-IO can be adapted to a variety of systems with different IP carriers. PCIe5IP, PCI5IP, cPCI4IP, PC104p4IP are a few examples. See Dynamic Data Sheet for more information plus downloadable Hardware and Software manuals.
7/2017 Added Support: IP-Parallel-Tape IP-Tape is a special version of IP-Parallel-TTL with a DTC tape machine interface. IP-Tape is now supported with a Win7 driver and reference application. IP-Parallel-Tape can be adapted to a variety of systems with different IP carriers. PCIe3IP, PCI3IP, cPCI2IP, PC104pIP are a few examples. See Dynamic Data Sheet for more information plus downloadable Hardware and Software manuals.
5/2017 New Design: PCIe4LHOTLinkx5 HOTLink is used in applications demanding high speed and high reliability including sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. PCIe4LHOTLinkx5 is a PCI Express card with 5 HOTLink receiver/transmitter pairs. Each of the HOTLink channels is supported with a separate DMA transfer engine plus local memory. All ports are full duplex with this design. The lower four ports are supported with a VHDCI connector. Fiber Optic controls are available on the connect to allow use in a Fiber System. The 5th port is supported with coax connectors. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames [indepedent each channel]. The first client version is optimzed for data reception from high speed A/D´s. Win7 driver and reference application available. See Dynamic Data Sheet for more information and manuals.
5/2017 New Design: PCIe8LXMCX2CB Adapt 1 or 2 XMC´s into a PCIe system with PCIe8LXMCX2. A 24 lane switch is used to provide 8 PCIe lanes to each of the XMC positions. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Internal XMC interconnect bus PCIe8LXMCX2CB is ported from PCIe8LXMCX2 and resistors added to allow for internal connections between the XMC Jn4/Jn6 connectors. 4 resistors at each Jn6 pin to allow connection between the XMC´s and or the SCSI/DIN connector IO. Almost zero stub length, matched length impedance controlled routing. Standard differential pair definitions. A detailed selection map is available in the manual. See Dynamic Data Sheet for more information and manuals.
5/2017 PMC BiSerial VI UART updated PMC BiSerial UART has been updated to include RTS/CTS flow control. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. Operational reference programmable on a port by port basis to be 32 MHz or user programmed PLL. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized and now an alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid mode where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® with Linux and VxWorks in development. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
5/2017 Product Update: IP-OptoISO-16
IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FET´s. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. IP-OptoISO-16 is configured to support high and low side switching. Each switch is independent for mixed mode operation. Win7, Linux, and VxWorks driver and reference application available. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Two Timer Counters which can be used for system timing or to create output waveforms. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-OptoISO-16 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
5/2017 Product Update: PCI2cPCI family
PCI2cPCI adapters allow the user to install a cPCI module into a PCI slot. A new version is available : PCI2cPCI-32-IO joins the PCI2cPCI-32 and PCI2cPCI-64 versions. The new -IO model provides headers connected to the cPCI module J2 IO signals. The headers can be accessed with standard header cables. A handy device for development and test situations. The cPCI module is installed externder card fashion - directly over the short connector adapter. All standard signals supported - DMA, Interrupts etc. Proper impedance on all signals. Extended area on PCB marked as no copper to support user modifications as needed. Please see the Dynamic Data Sheet for links to HW manual and detailed information.
4/2017 Product Update: IP-OptoISO-16
IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FET´s. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. IP-OptoISO-16 is configured to support high and low side switching. Each switch is independent for mixed mode operation. Win7 and Linux driver and reference application available. VxWorks in development. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Two Timer Counters which can be used for system timing or to create output waveforms. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-OptoISO-16 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
4/2017 PMC BiSerial VI UART updated PMC BiSerial UART has been updated with a port by port option to use the on-board PLL. More frequencies can be generated between the options for 32 MHz reference and 4 PLL inputs. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. Operation from 2 MHz down. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized and now an alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid mode where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® with Linux and VxWorks planned. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
4/2017 New Release: PCIe4LXMCX1 Available now. Adapt an XMC into a PCIe system with PCIe4LXMCX1. 4 PCIe lanes routed to the XMC. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Ported from the popular 8 PCIe lane version PCIe8LXMCX1 to allow users to implement in the shorter x4 PCIe positions when their XMC does not use 8 lanes. See Dynamic Data Sheet for more information and manuals.
4/2017 IP-Parallel-HV IP-Parallel-HV incorporates 24 open collector drivers to allow a wide range of external voltages to be controlled. A local regulator can be programmed for voltages up to 12V, and an external reference used for voltages up to 30V. Resistor networks divide the external voltages to allow 24 0-30V inputs to be accepted. Programmable interrupts on each receiver. Updated SW is now available for Windows, Linux and VxWorks. There is plenty of room in the FPGA for custom filtering etc. IP-DEBUG-BUS is a recommended accessory.
3/2017 PMC BiSerial VI UART PMC BiSerial UART has been updated and moved to the PMC BiSerial VI platform. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. 32 MHz reference frequency allows operation from 2 MHz down to 150. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized and now an alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® with Linux and VxWorks planned. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
2/2017 PC104p Chassis web page now has two "movies" showing disassembly and assembly of the external and internal chassis. The chassis are designed to house multiple PC104, PCI-104, PC104p, PCIe104 devices. A rugged container suitable for harsh environments. Power Supplies, Fan cards, IO and other support available.
2/2017 PMC-MC-X2 and PMC-MC-X4 Chassis web page now has two "movies" showing disassembly and assembly of the chassis. The chassis are designed to house two or four PMC devices. The PMC´s are mounted on the top and bottom of the motherboard for high density packaging. The motherboard supports the basic PCI functions with power supplies, arbitration, interrupt routing, fan cooling with speed control etc.
Front and Rear View of 2 position RIO version of the PMC Mini Carrier Chassis
2/2017 IP-BiSerial-VI is Dynamic Engineering´s latest IndustryPack®. It is FPGA based with 24 independent differential IO each with programmable termination. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. Industrial Temperature range. 8 and 32 MHz IP Module operation. Windows, Linux, and VxWorks drivers and reference software. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Two models released - CTRB with software selectable Counter Timer and One-Shot modes - 8 ports per module, and SIB with two software selectable serial interfaces.
11/2016 VPX2IP is Dynamic Engineering´s latest PCIe native FPGA based IndustryPack Module adapter/carrier - this time for VPX. VPX2IP is a 3U 4HP mechanical configuration with two IP Module locations. Front Panel IO is standard utilizing two 50 position box headers with ejectors at the VPX bezel. Compatible with standard 50 pin ribbon cable and discrete wiring systems. Rear Panel IO is also available with IP module IO routed to the VPX rear connector [P2/J2]. Multi-word transfers are supported: 64, 32, 16, and 8 bit transfers are easy to implement with standard CPU´s. VPX2IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range, 8 and 32 MHz IP Module operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. PCIe single lane operation. Windows, Linux, and VxWorks drivers and reference software. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
11/2016 PCIe104Diff is a new PCIe native FPGA based design providing DMA or standard R/W operation. "DIFF" provides 18 differential transceivers which can be populated with LVDS or RS-485 compliant [or a mix] interface devices. The FPGA is supported with SDRAM, triple output PLL, and oscilator. The transceivers are fully suported for independent operation with programmable termination and direction for each transceiver. Stackable technology. PCIe adapter is available for use within a PC. The initial client design "OS1" uses a serial interface operating at 150 MHz. Linux, and Windows SW packages. See Dynamic Data Sheet for more information and manuals.
11/2016 PCIe1LPCIe104 is a new PCIe adapter board to allow mounting a 1 lane PCIe104 device in a standard PC. Two positions are provided to allow operation in a production orientation - PCIe legal mechanical, or in a test orientation with the PCIe104 device mounted above the extender card for ease of access. The PCIe interconnection is through a Gen 3 mux to prevent stubs to the unused position. Local power supply for the 5V rail on the PCIe104. 1/2 length PCIe card with option for zero slot fan. Gen1-3 PCIe supported. See Dynamic Data Sheet for more information and manuals.
10/2016 DESWBO now includes an International power supply. Adapters for many common non-US systems are accomodated with the included adapters. DESWBO is the Dynamic Engineering SpaceWire BreakOut and is used for monitoring and debugging SpaceWire links. DESWBO is inserted between two nodes to track FCT´s, various error conditions, traffic being passed. Test points are provided for direct monitoring of the received SpaceWire signals.
See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Combined with the IP Module driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
9/2016 cPCI2IP Win7 unified driver released for cPCI2IP. Driver comes with install files for driver plus reference software using cPCI2IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of cPCI2IP. Supports new features with Rev G1 FPGA. PROM updates are available.
See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Combined with the IP Module driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
9/2016 Product Update: IP-OptoISO-16
IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FET´s. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. IP-OptoISO-16 is configured to support high and low side switching. Each switch is independent for mixed mode operation. The new revision 04 of the PCB supports the Spartan II FPGA. The new FPGA can support additional client requested functionality. The new design is compatible with the previous revisions. Win7 driver and reference application available. Linux and VxWorks in development. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Two Timer Counters which can be used for system timing or to create output waveforms. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-OptoISO-16 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
9/2016 Updated Design: PCIe8LXMCX2 Adapt 1 or 2 XMC´s into a PCIe system with PCIe8LXMCX2. A 24 lane switch is used to provide 8 PCIe lanes to each of the XMC positions. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Now updated to allow user selection of delayed, immediate, and disabled for the +5V and +3.3V internal power supplies. If your XMC does not use one of the rails your inrush requirement can be reduced by disabling the unused supply. If your system has slow to program devices you will want the immediate turn on setting, and if your device is faster to load you can space out the inrush of the local supplies with the delayed setting. See Dynamic Data Sheet for more information and manuals.
9/2016 Updated Design: PCIe8LXMCX1 Adapt an XMC into a PCIe system with PCIe8LXMCX1. 8 PCIe lanes routed to the XMC. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Now updated to allow user selection of delayed, immediate, and disabled for the +5V and +3.3V internal power supplies. If your XMC does not use one of the rails your inrush requirement can be reduced by disabling the unused supply. If your system has slow to program devices you will want the immediate turn on setting, and if your device is faster to load you can space out the inrush of the local supplies with the delayed setting. See Dynamic Data Sheet for more information and manuals.
9/2016 Updated Design: PCIe4LHOTLinkx6 HOTLink is used in applications demanding high speed and high reliability including sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. PCIe4LHOTLinkX6 is a PCI Express card with 6 HOTLink receiver/transmitter pairs. Each of the HOTLink channels is supported with a separate DMA transfer engine plus local memory. The lower 4 channels are 1/2 duplex and the upper 2 full duplex. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames [indepedent each channel]. Win7 driver and reference application available. Linux and VxWorks in development. See Dynamic Data Sheet for more information and manuals.
8/2016 IP-429-II Use IP-429-II to interconnect with your ARINC 429 Bus. Act as a transmitter and/or receiver with up to 4 Transmitters and 8 receivers per IP device. Standard and custom frequencies on the 429 bus. FIFO support on transmitter. Win7 driver and reference application available. Linux and VxWorks in development. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Time Tagging of received data with 32 bit tag, 1 uS resolution. LW aligned transmit and receive ports to optimize 32 bit auto-incrementing accesses. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-429 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
8/2016 IP-HV-TEST Use IP-HV-TEST to develop a driver or test an IP Carrier, IP-HV-TEST is based on the IP-Parallel-HV IndustryPack module with a special FLASH load. The Module responds to all 4 access types, allows testing of both interrupts, has 2K bytes of RAM and more to support your SW or HW development. IO, INT, MEM and ID spaces are supported along with interrupts etc. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module. IP-DEBUG-BUS is a recommended accessory.
7/2016 IP-Generic Win7 manual for is now posted on each of the 8 IP Carrier pages with Win7 support. IP Generic allows the client to communicate with IP Modules not supported with specific IP Drivers. IO, INT, MEM and ID spaces are supported along with interrupts etc. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module.
7/2016 PCIe3IP Win7 unified driver released for PCIe3IP. Driver comes with install files for driver plus reference software using PCIe3IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 3 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCIe3IP.
6/2016 PC104pIP Win7 unified driver released for PC104pIP. Driver comes with install files for driver plus reference software using PC104pIP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PC104pIP.
6/2016 PCIe5IP Win7 unified driver released for PCIe5IP and first units of PCIe5IP shipped. Driver comes with install files for driver plus reference software using PCIe5IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 5 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCIe5IP.
5/2016 PMC-MC-X2-RIO-BA25 Configured version of chassis / motherboard using 2020 based CPU and HDLC interface to create an ethernet / HDLC bridge for remote HDLC configuration, control and data transfer. See under Customized tab on Dynamic Data Sheet for PMC-MC-X2 Chassis. Linux applications developed with Ubuntu. Targeted application is HDLC ⇆ Ethernet [local or long haul]⇆HDLC with the BA25 taking care of the HDLC⇆Ethernet conversion on each end. A packet Server application was developed to manage the traffic between the BA25´s.
5/2016 PC104p4IP Win7 unified driver released for PC104p4IP. Driver comes with install files for driver plus reference software using PC104p4IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 4 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PC104p4IP.
5/2016 cPCI4IP Win7 unified driver released for cPCI4IP. Driver comes with install files for driver plus reference software using cPCI4IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 4 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of cPCI4IP.
5/2016 cPCI2IP Win7 unified driver released for cPCI2IP. Driver comes with install files for driver plus reference software using cPCI2IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for both positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of cPCI2IP.
5/2016 PCI3IP Win7 unified driver released for PCI3IP. Driver comes with install files for driver plus reference software using PCI3IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 3 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCI3IP.
5/2016 PCI5IP Win7 unified driver released for PCI5IP. Driver comes with install files for driver plus reference software using PCI5IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 5 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCI5IP. PCI5IP has recently been qualified in the Magma external chassis. Overnight testing with multiple PCI5IP´s each with IP-Test installed. More than 3 million memory tests performed per card without issue. [Billions of operations over the course of the walking ones etc.]
3/2016 PMC-MC-X2 Manual released for Rear IO version. - PMC-MC-X2 has a new version featuring rear IO. VHDCI connectors are used along with matched length, impedance controlled, differential routing from Pn4 of each PMC position to the rear of the motherboard. In addition the power supplies have been updated to handle 10-40V input power. Temperature based Fan control for 12V fans. The standard features for arbitration, PCI clock generation, interrupt handling etc. are retained. An updated version of the chassis is also available with the rear IO and rear status LED´s. PMC-MC-X2 has two PMC positions where the intallation is back-to-back sandwiching the motherboard. The overall package is not much larger than the two PMC´s. Install a PrPMC in position 0 and your IO device in Position 1 for a compact, rugged, industrial temp [depending on PMC´s] solution.
2/2016 PCIe8LXMCX2 has been updated. New features include (1) option of having either, neither or both rear IO connectors [J6, J4] installed (2) user shunt selection to enable or disable the 3.3V and 5V power supplies independently, and to select a delayed or immediate start-up for those power supplies. A delayed start-up can help reduce in-rush requirements in your system while immediate start-up may be desired for fast embedded systems. PCIe8LXMCX2 is an 8 lane PCIe compatible board with 2 XMC positions. The PCIe "gold finger" connections are routed to the switch and to the XMC´s with impedance controlled differential traces. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4/Pn6 to either DIN or SCSI connector. Available now.
2/2016 Windows® Driver for BA16 An updated driver for the BA16 version of the PMC-Parallel-TTL and XMC-Parallel-TTL designs has been released. The updated driver is optimized for WDF [Windows 7 and later] projects and includes the driver, installation files, and reference application. BA16 has the standard features of PMC-Parallel-TTL plus: two synchronous parallel ports - 8 bits with reference clock and strobe. DMA support with 4Kx32 FIFO on RX, and 2Kx32 FIFO on TX. Driver has utilities for programming the PLL using the "JED" file. The driver is included with purchase of PMC-Parallel-TTL-BA16 or XMC-Parallel-TTL-BA16.
2/2016 SpaceWire Cables Two new versions have been released bringing the total variations of our SpaceWire cables to 11 types. The basic SpaceWire cable is male to male with TX-RX cross-over incorporated. Variations include male-to-female with 1:1 wiring to support bulkhead implementations, various plating options, male-to-female with cross-over etc. All can be ordered to custom length requirements.
2/2016 PCI-ALTERA Win7 driver - PCI-Altera is a user programmable design featuring 40 differential IO [can be 485 or LVDS] 12 TTL IO, 8 PLL´s 8 TX and 8 RX channels with DMA support. PCI-Altera has a 20K400E Altera device for the user design. [ PCIeAlteraCycloneIV is recommended for new designs.] Many clients have PCI-Altera installed into systems requiring OS updates. New Windows® 7 compliant driver and user application packages are available to support these legacy systems. A limited number of PCI-Altera boards are available for purchase. PCIeAlteraCycloneIV is production status.
2/2016 PMC-MC-X2 Updated Version - PMC-MC-X2 has a new version featuring rear IO. VHDCI connectors are used along with matched length, impedance controlled, differential routing from Pn4 of each PMC position to the rear of the motherboard. In addition the power supplies have been updated to handle 10-40V input power. Temperature based Fan control for 12V fans. The standard features for arbitration, PCI clock generation, interrupt handling etc. are retained. An updated version of the chassis is also available with the rear IO and rear status LED´s. PMC-MC-X2 has two PMC positions where the intallation is back-to-back sandwiching the motherboard. The overall package is not much larger than the two PMC´s. Install a PrPMC in position 0 and your IO device in Position 1 for a compact, rugged, industrial temp [depending on PMC´s] solution.
12/2015 HDEterm68 Updated Version - HDEterm68 now has internal planes to provide impedance controlled routing for better perfomance. Matched length, differentially routed, impedance controlled traces from SCSI to breakout to SCSI. Options for horizontal and vertical connectors plus mixed as well as with a DIN rail enclosure or for stand-off mounting. The ENG version has strategically placed footprints to allow for termination, isolation, signal injection, plus footprints for an oscillator, differential transceiver [RS485, LVDS], and more. A popular board with uses in loop-back testing, break-out for plant / system operation, system simulation etc.
12/2015 PCI-NECL-II-STE3A Re-Engineered - "STE3A" 8 bit parallel data path - full duplex - [NECL input and output] with reference clock and enable. Data valid on falling edge of clock, enable active high. Programmable boundary SDRAM configured as FIFO (32 Mbytes), DMA support, 12 bits GPIO (TTL). Updated with higher performance memory operation, increased FIFO size, added status, and operational enhancements. Linux Drivers plus reference applications available - including multi-board support. Manuals are available on the Dynamic Data Sheet. Cross over and straight connection D100 cables are available.
10/2015 PMC BiSerial III New version - "SDLC" SDLC provides 8 full duplex channels of Synchronous Data Link Control interface. Each channel has separate 4K Byte Rx and Tx Dual Port RAM based circular buffers. Linux and Windows Drivers plus reference applications available. Manuals are available on the Dynamic Data Sheet.
9/2015 PCIeBiSerialDb37 New version - "L3COM1" L3COM1 provides a byte wide half duplex port with flow control. LVDS IO is standard. More than 1 MByte of storage for the receive direction. DMA. PLL programmable for a range of frequencies. Packetized and FIFO level based operation. Packets allow for byte length programming while retaining the advantages of LW packed data. Programmable padding between received packets. Tested at 40 MHz. Hardware and Linux support manuals are available on the Dynamic Data Sheet.
8/2015 PCIe3IP Updated PCIe3IP is ready to order. Now even faster. Multi-word transfers are now supported, incorporating the 32 bit to 16 bit conversion familiar from the PCI3IP, PCIe3IP also handles longer transfers up to 64 words. 64, 32, 16, and 8 bit transfers are easy to implement with standard CPU´s. PCIe3IP is a 3 position adapter for IndustryPack devices. PCIe3IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range, 1/2 length, 8 and 32 MHz operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. PCIe single lane operation. Compatible with standard 50 pin ribbon cable and discrete wiring systems. Linux and Windows drivers and reference software available. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS.
6/2015 PMC XM DIFF has been updated. PMC XM DIFF is designed for client designed applications. PMC XM DIFF has a built in PCI interface with DMA to support the client design within a Virtex LX60. The recently updated design has improvements for manufactability, through-put, programming options and additional status. Supported with Windows®7 drivers, reference application SW and starter design [VHDL]. 34 differential pairs with RS485, LVDS or a mixture. Option for Bezel or Rear IO. Matched length, impedanced controlled IO routing. Includes temperature sensor, and user Dip Switch. Available now. Linux and VxWorks coming
6/2015 PCIe8LXMCX1 PCIe8LXMCX1 has been updated. New features include (1) option of having either, neither or both rear IO connectors [J6, J4] installed (2) user shunt selection to enable or disable the 3.3V and 5V power supplies independently, and to select a delayed or immediate start-up for those power supplies. A delayed start-up can help reduce in-rush requirements in your system while immediate start-up may be desired for fast embedded systems. PCIe8LXMCX1 is an 8 lane PCIe compatible board with 1 XMC position. The PCIe "gold finger" connections are routed to the XMC with impedance controlled differential traces. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4/Pn6 to either DIN or SCSI connector. Available now.
4/2015 PCIe8LSwVPX3U The switched version of PCIe2VPX3UX4 is now available. PCIe8LSwVPX3U is an 8 lane PCIe adapter with switch isolation for VPX development. The switch isolates the spread spectrum clocking found in most PC´s from the VPX port. PCIe 3.0 compliant, 1-8 lanes can be used by the installed VPX. Local power conversion for the 3.3V and 5V rails with efficient switching power supplies. Secondary power connector can be installed for high power consumption VPX cards. 10A on 3.3V and 5V rails max. Power monitoring circuits on the VPX and switch power rails. Status indicators for switch. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS. Available now.
3/2015 PCIe3IP The PCIe version of PCI3IP is now available. PCIe3IP is a 3 position adapter for IndustryPack devices. PCIe3IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range, 1/2 length, 8 and 32 MHz operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. 32 bit accesses are automatically processed with dual IP operations. PCIe single lane operation. Compatible with standard 50 pin ribbon cable and discrete wiring systems. Linux and Windows drivers and reference software available. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS.
3/2015 SpaceWire "BK" The PCI version of SpaceWire has a new update available BK. Version BK make use of the greater resources in the Spartan 6 FPGA to increase FIFO size, increase top speed, provide Industrial Temperature operation, and add new features. Add "-BK" to the PN to receive the BK version. Revision K will continue to be available for clients with on-going projects. The SpaceWire drivers are updated to provide Windows, Linux, VxWorks support for model BK. The PMC, ccPMC, PCI-104 models will be enhanced to offer BK functionality. For more details please download the hardware manual for the BK version. Available on the SpaceWire summary page.
3/2015 New HW Release VPX-6U-COOL joins VME-6U-COOL to provide cooling to VPX and VME 6U hardware. Up to 12 FAN´s mounted per board with options for direction, voltage, location, zero slot or high velocity. Other versions available for cPCI and PC104/PCI-104.
1/2015 New Driver Release PCIeAlteraCycloneIV Windows 7 compliant 32 and 64 bit drivers along with UserAp reference software have been released. Windows and Linux Driver Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PCIeAlteraCycloneIV along with reference software showing how to use the drivers to control the User design. PCIeAlteraCycloneIV features 16 DMA channels to support user designs based on RS-485 or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the PCIe bus and the user has access to the Cyclone IV FPGA for their IO driven design. 40 differential pairs and 12 TTL IO are available to the user along with multiple PLL´s.
12/2014 Updated Manual Release PCIe4LHOTLinkx6 Revision A of the Windows Driver and Revision 2.0.0 of the Linux Driver Manuals have been released. Both drivers are available to clients of PCIe4LHOTLinkx6 along with reference software showing how to use the drivers to control the HOTLink design. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. PCIe4lHOTLinkx6 features up to 6 HOTLink connections with PECL or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the HOTLink transmitters/receivers. The base version has programmable sync patterns [up to 3 characters in series to cause sync to be achieved], deep FIFO´s, independent DMA operation for each channel, PLL support and more. One RJ45 connector has 4 half duplex connections, and the other 2 full duplex connections.
12/2014 Updated Driver Release SpaceWire Windows 7 driver for revisions up to K. The driver and reference software are used with Dynamic Enginerering SpaceWire interface hardware including ccPMC-SpaceWire, PMC-SpaceWire, PCI-SpaceWire, PCI-104-SpaceWire. Linux and VxWorks drivers and reference software are also available for revision K SpaceWire hardware.
12/2014 Updated Manual Release PCIe4LHOTLinkx6 Revision C of the Hardware manual has been released. Please refer to the HW manual for memory maps, bit maps, operational descriptions, capabilites, pinouts etc. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. PCIe4lHOTLinkx6 features up to 6 HOTLink connections with PECL or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the HOTLink transmitters/receivers. The base version has programmable sync patterns [up to 3 characters in series to cause sync to be achieved], deep FIFO´s, independent DMA operation for each channel, PLL support and more. One RJ45 connector has 4 half duplex connections, and the other 2 full duplex connections. Windows and Linux drivers and reference software available.
10/2014 Updated Product Release PCI2PMC Industry standard passive PMC adapter for PCI bus installations has been updated to revision K. Now Shipping. New additions to the feature list include user selectable grounding options for the PMC and PCI bezels [separately], enhanced header placement, and miscellaneous manufacturing updates. Please refer to the manual [PDF] for more information.
9/2014 New Product Release PCIe4LHOTLinkx6 features up to 6 HOTLink connections with PECL or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the HOTLink transmitters/receivers. The base version has programmable sync patterns [up to 3 characters in series to cause sync to be achieved], deep FIFO´s, independent DMA operation for each channel, PLL support and more. One RJ45 connector has 4 half duplex connections, and the other 2 full duplex connections. Windows and Linux drivers and reference software available.
9/2014 Updated Product Release PCIBPMCX1 has been updated for improved fan placement, improved performance, and improved manufacturability. PCIBPMCX1 uses a PCI/PCI-X bridge to interconnect the installed PMC and the computer bus. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The Pn4 connector is routed to a SCSI connector with matched length differential routing and 100 ohm impedance.
9/2014 Updated Product Release PCIBPMCX2 has been updated for improved fan placement, improved performance, and improved manufacturability. PCIBPMCX2 uses a PCI/PCI-X bridge to interconnect the installed PMC´s and the computer bus. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The Pn4 connectors are routed to either an installed SCSI or DIN connector with matched length differential routing and 100 ohm impedance.
9/2014 New Product Release SCSI-to-SpaceWire is a cable adapter designed to connect between the "X1" line of PMC carriers and SpaceWire hardware. The cable allows SpaceWire nodes with internal to the chassis connections to be used internal to the chassis or brought out to a bezel, bulkhead or other intermediate device. User defined lengths, finishes, and SpaceWire node selection.
6/2014 Updated Product Release PC104p2PMC is an adapter to allow the use of a PMC board in a PCI-104 or PC104/p system. Dynamic Engineering has updated the design to include a path for the PMC rear IO [Pn4]. Matched length, impedance controlled differential traces connect Pn4 with P1 [SCSI]. An updated hardware manual is available on the Dynamic Data Sheet including an interconnection table. PC104p2PMC allows users to add a PMC to their PCI-104 stack. Bezel and rear IO supported. PC104p2PMC is a passive design. 4 stack postions are supported with switch control.
6/2014 Updated Product Release PMC-BiSerial-III-HW2 Dynamic Engineering has updated the HW2 version of PMC BiSerial III to improve SDLC performance. Changes include updating the Dual Port RAM memory manager to allow for continuous operation. HW2 has SW programmable operation with support for SDLC, Async [UART], and HW1 protocols. Conformal coating and ROHS processing options. Win32 and Linux support. Win7 driver coming. Ask for VxWorks.
3/2014 Updated Product Release PCIBPMCX2 Dynamic Engineering has updated PCIBPMCX2 for better manufacturability and long term support. PCIBPMCX2 is an adapter / carrier for PMC´s with 2 positions on a full size PCI card. The PCI-X capable and PCI compatible bridge allows for local PCI traffic behind the bridge as well as Host interaction with the mounted PMC devices. Perfect for real time processing with a local PrPMC and IO device. PCI slots are getting harder to find, add two PMC's in one PCI slot with PCIBPMC. This update demonstrates Dynamic Engineering´s long term commitment to our clients.
2/2014 Updated Product Release ccPMC-HOTLink Dynamic Engineering has updated ccPMC-HOTLink to use a Spartan 6 FPGA providing a large boost in available gates, internal memory, and IO rates. The design is extended temperature. The first clientized version is the AP1 which focused on image capture applications. 64Kx32 receive and transmit internal FIFO´s supported with scatter-gather capable DMA. Conformal coating and ROHS processing options. Win7 driver available with options for Linux and VxWorks.
2/2014 New Product Release cPCIRepeat32 Dynamic Engineering has released cPCIRepeat32 - an extended temperature PMC carrier with PCI bus expansion. cPCIRepeat32 has a 32 bit connection to the PCI bus on cPCI J1. J2 is used to provide the secondary side of the local bridge to the backplane along with Clocks, Bus Arbitration etc. Available with or without J2 installed. Standard and ROHS options.
1/2014 New Product Release BA23 Dynamic Engineering has released the BA23 version of PMC BiSerial III. This implementation is a variant of the BAE9 design with channels 6 and 7 updated to provide a 32 bit 5 MHz UART function. Channels 6&7 have FIFO support with DMA. Programmable for frequency, parity, stop bits. Interrupt or polled opertation. Channels 0-5 have the "BAE9" capabilities. RAM based with multiple triggering options. Linux driver support.
12/2013 New Product Release BA22 Dynamic Engineering has released the BA22 version of PCIeBiSerialDb37. The design is for image data transmission. LVDS, 73.636 MHz, 2 bit serial with reference clock and sync. The transmit side has ~262Kx32 of FIFO storage, programmable line length, idle length, number of lines per frame, minimum data to start transmission, and transmission rate. An receiver is also supplied with 5Kx32 FIFO storage, Sync detection, Frame Marking, and other features. DMA on both the Rx and Tx channels.
11/2013 New Driver Release Linux driver is now available for use with PCIeAlteraCycloneIV. Validated on an i7 Ubuntu SMP server running version 3.8.0-33 x86_64 kernel (64 bit). Driver and Reference application support all operational modes. PCIeAlteraCycloneIV features a user configuratble/programmable Cyclone IV 115 device supported with 8, 3 port PLL devices, 40 differential IO, 12 TTL IO, FLASH, and 8 high speed bidirectional data links between the PCIe interface and user design. DMA is supported on all 16 channels independently. Load the Altera from FLASH [built in] or via real-time file loading. Free to Dynamic Engineering PCIeAlteraCycloneIV clients. Contact sales@dyneng.com.
10/2013 Product Release PcieAlteraCycloneIV has been released to manufacturing status. PCIeAlteraCycloneIV features a user configuratble/programmable Cyclone IV 115 device supported with 8, 3 port PLL devices, 40 differential IO, 12 TTL IO, FLASH, and 8 high speed bidirectional data links between the PCIe interface and user design. DMA is supported on all 16 channels independently. Load the Altera from FLASH [built in] or via real-time file loading. Reference VHDL, software, and drivers are available along with cables and breakouts for the "D100" connector. PCIeAlteraCycloneIV has similar base features to the PCI-Altera design and should be considered for an upgrade. Differential IO can be outfit with RS485 or LVDS or a mix of the two. Driver and reference software are available for Win32 with VxWorks, Win7 and Linux in development. PCIeAlteraCycloneIV is available now.
10/2013 Updated Manual Release SpaceWire Hardware Manual has been updated with the latest design implementation information.
9/2013 Updated Product Releases cPCIBPMC3U64ET and cPCIBPMC6UET have been updated to incorporate LC filtering on the 5V and 3.3V power rails. Some cPCI systems suffer from noisy power distribution leading to unstable operation with the add-in cards. cPCIBPMC3U64ET and cPCIBPMC6UET now incorporate LC filters on the two main power rails. The carriers allow PMC devices to be installed into cPCI systems. Both designs are industrial "ET" temperature rated. Zero Slot Fans are available.
8/2013 New Hire Dynamic Engineering welcomes Brian Davis to the engineering department. Brian is a Sr. Engineer with years of experience in the embedded market. Brian will help to expand our PCIe based design capabilities and product line.
8/2013 Updated Product Release VxWorks driver has been updated to the current VxWorks and SpaceWire revisions. Feature expansion, misc. clean-up and enhanced interrupt processing are the benefits of the new release. Free to Dynamic Engineering SpaceWire clients. Contact sales@dyneng.com.
7/2013 Updated Product Release Win7 Driver has been updated. Feature expansion, misc. clean-up and enhanced interrupt processing are the benefits of the new release. Free to Dynamic Engineering SpaceWire clients. Contact sales@dyneng.com.
7/2013 Updated Product Release HDEterm100 has been updated for better performance. Power and Ground planes have been added and the signal routing updated to be differential with impedance control, length matching. User selectable shield to ground plane connections with AC, DC, and open for each connector. In addition more options are available for voltage division and other termination schemes.
7/2013 Updated Product Release cPCIBPMC3U64ET has been updated for better performance. Power filtering on 5V and 3.3V for noisy cPCI environments. Updated 0402 capacitors for better decoupling of bridge power supplies. Now with optional "Zero Slot" fans.
7/2013 Updated Product Release cPCIBPMC6UET has been updated for better performance. Power filtering on 5V and 3.3V for noisy cPCI environments. Updated 0402 capacitors for better decoupling of bridge power supplies. Now with optional "Zero Slot" fans.
6/2013 Updated Product Release cPCI2PMC has been updated for better manufacturability. Moving to 0402 isolators allowed for shortened trace lengths. Increased current available to the PMC position. Versions with PCI32, PCI64, rear IO, Slot Zero still available. Now with optional "Zero Slot" fans.
6/2013 New Product Release PMC-BiSerial-III-HW2 has a new Linux driver available. IOCTL based Win32 drivers are also available. The HW2 version implements 8 channels of the HW1 protocol, plus 24 blocks of Asynchronous or SDLC IO. The SDLC takes 4 blocks per channel and the Asynchronous takes two. Each HW1 channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 blocks. The SDLC channels are programmable for frequency using the PLL. The Asynchronous channels are designed with a UART style protocol.
3/2013 Updated Product Release PMC-BiSerial-III has a new clientized version "BAE9" 8 10.4 Mhz UART channels with multiple trigger and retransmit capabilities. High performance driver for Linux plus IOCTL based Win32 and Win7 drivers are available.
3/2013 New Product Enhancement: Customerized version The PMC-Parallel-TTL design has been updated with a user specific version. The
1/2013 Product Development PMC XM DIFF is currently in development for a VxWorks driver. PMC XM DIFF has 34 differential IO and can be configured with RS485 or LVDS IO. User designs are loaded into a Virtex 4 FPGA - SX35 or LX60. Windows support is currently available.
1/2013 Product Release XMC Parallel TTL VxWorks Dynamic Engineering now has VxWorks support for the XMC Parallel TTL. The version supported at this time is BA16. Initial CPU target was our new FreeScale 2020. XMC Parallel TTL has 64 bidirectional IO lines. The BA16 version is configured to support two, 8 bit parallel ports with reference clock and alignment strobe.
10/2012 Shipped SpaceWire Revision I FLASH has been released. Power Management Capability has been incorporated into the configuration space. For systems using virtualization this feature is important. Other miscellaneous updates to handle situations where multiple EEP codes are received. Dynamic Engineering has SpaceWire for PMC, PCI, PC104p and with adapters supports PCIe, VME, cPCI, VPX and other board formats. Win7, Win32, Linux drivers are available.
10/2012 New Capability Dynamic Engineering has added VxWorks to our capabilities. We have purchased the "All Types" license to allow us to develop BSP´s for our products and target any supported CPU. It takes more than a license. Dynamic Engineering has VxWorks experienced Software Engineering talent on staff. Please contact us to develop a BSP for you. Our first project is a custom BSP for a "Modbus" version of the PMC-BiSerial-III.
9/2012 Shipped XMC-Parallel-TTL is now a production status board. Available now. XMC-Parallel-TTL is an XMC version of the PMC-Parallel-TTL. Common IO connector definitions make it easy to support multiple projects with similar software and cables for both PMC and XMC. Front and rear IO options, PLL, COS interrupts, flexible VPWR [+12 or +5 is fine]. The FPGA can be updated for client specific versions. 1-4 lane PCIe operation.
8/2012 Shipped PCIe8LXMCX1 is now a production status board with it´s first deliveries. Available now. PCIe8LXMCX1 is an 8 lane PCIe compatible board with 1 XMC positions. The PCIe "gold finger" connections are routed to the XMC with inpedance controlled differential traces. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4 to either DIN or SCSI connector.
7/2012 Shipped PCIe8LXMCX2 is now a production status board with it´s first delivery of 24 units. Available now. PCIe8LXMCX2 is an 8 lane PCIe compatible board with 2 XMC positions. A 24 lane switch is used to route the PCIe interface to the XMC positions. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4 to either DIN or SCSI connector.
7/2012 Updated Product Release PCIBPMC is now an "ET" rated board standard. Components rated for -40 to +85C operation. Options for DIN or SCSI rear IO, Conformal coating and "Zero Slot Fans". Available now.
6/2012 Updated Product Release PMC-BiSerial-III has a new clientized version "BAE9" 8 10.4 Mhz UART channels with multiple trigger and retransmit capabilities. Win32 and Win7 drivers available. Available now.
6/2012 Updated Product Release IP-429-II is available in 4 configurations with 1,2,3 or 4 transmitters coupled with 2,4,6 or 8 receivers. Time Tag is now standard. Industrial Temperature Standard. Arinc 429 protocol. IndustryPack format card. 8 / 32 MHz IP bus operation. New lower price with more features than the original design. Available now.
6/2012 New Product Release PCIe2VPX3UX4 is ready to help you with your VPX development. Take advantage of your PC resources by hosting your VPX in a standard PCIe slot. PCIe2VPX3UX4 routes 4 PCIe lanes to the P1 VPX connector plus power to P0 and the user IO on P2 to a SCSI connector on the PCIe2VPX3UX4. 5V and 3.3V are produced with on-board power supplies for the VPX. +12V is routed from the PCIe interface. JTAG and Global Adressing support included. PCIe and P2 differentially routed with 100 ohm controlled impedance and matched lengths. Available now.
6/2012 New Product Release VPX-RCB is a "kitchen sink" design with everything you need to control digital receivers, measure voltages, take temperatures, receive high voltage signals and more. Please go to the Dynamic Data Sheet for a more complete description, photo, block diagram, and HW manual. Available now.
4/2012 Driver Update SpaceWire has an updated driver and reference software set : Linux kernal version 3.0.0-17 developed on Ubuntu distribution 11.10. Available free of charge to our SpaceWire clients. Works with PMC, PC104p and PCI SpaceWire versions.
4/2012 Driver Update ccPMC-HOTlink has an updated driver and reference software set : Linux kernal version 3.0.0-17 developed on Ubuntu distribution 11.10. Available free of charge to our PMC-HOTlink clients.
3/2012 New hires Dynamic Engineering has hired Thai Nguyen to work in the engineering group. Thai has more than 15 years of Embedded Design experience post MS. Thai is working on our update to the PCI-Altera known as PCIeAlteraCycloneIV.
1/2012 New Product Release Take the worry out of fielding your hardware. A reversed reference supply can cause a lot of damage in unprotected systems. PC104p-RPP provides Reverse Power Protection for power supplies in PC104, PCI-104, PC104p and stand-alone applications. PC104p-RPP uses FET technology to provide the protection while significantly reducing the voltage drop. "RPP" has an optional fan to aide in system cooling. Available now.
12/2011 New Product Release Windows 7® driver. Dynamic Engineering has written a Windows 7 compliant driver for the PCIe-BiSerial-DB37-RTN8 design. The driver supports standard target accesses as well as DMA. The driver is provided with a reference application to speed integration. The driver is free to clients who have purchased RTN8.
10/2011 New Product Release SpaceWire INtime Driver. Dynamic Engineering has written a driver for the TenAsys INtime real-time operating system. The driver comes with a set of reference software to speed your integration. Please see the SpaceWire Dynamic Data Sheets for more information.
10/2011 New Product Release PMC-BiSerial-3T20 is ready for your application. Based on the proven PMC-BiSerial-III, the "3T20" has 20 transformer coupled and 2 direct coupled RS-485 IO with several termination options, large SDRAM based FIFO capability, and a Spartan III FPGA with plenty of room for your application. The first clientized version "HW1" has shipped - 20 manchester encoded / decoded data streams with a dual port RAM interface.
7/2011 New Product Release PCIeBPMCX2 is ready for your application. Based on the proven PCIeBPMCX1 and ported from the PCIBPMCX2 [PCI version]; the 2 PMC slot carrier can handle your embedded computing requirements. Use a local prPMC and specialized IO together in the same slot while retaining higher level control for an expandable system architecture with real time capabilities. Alternatively, pack two PMC IO cards into one PCIe slot to save system resources.
PCIe with 4 lanes, power supplies with 9.5A on the 5V and 3.3V rails, 2 PMC positions, Zero Slot fan options, options for Ethernet and Serial ports for prPMC position, programable interrupt routing, bezel and internal IO. Please refer to the Dynamic Data Sheet for more information. Extensive load testing has been performed to verify the design and characterize operation.
6/2011 Product Release PC104p-COOL New design to add cooling fans using "Zero Slot"™ technology to your PC104, PC104p or PCI-104 stack. 5V or 12V fan operation. Reversible. First deliveries July 2011.
6/2011 Product Release PCI-ECL-II New revision to the PCI-ECL design. Recommended for new designs. Spartan 6 FPGA with PCI interface, DMA and IO state-machines. 64 Mbytes of SDRAM on board. 20 ECL out and 20 ECL in. 12 TTL IO. Phase Locked Loop with 4 programmable clocks. SDRAM can be configured as a large FIFO with programmable boundaries. Initial client design for byte wide parallel interface with bursted clock and Windows® driver delivered. Please see the Dynamic Data Sheet for more information.
5/2011 Product Release 64 bit Linux driver released for SpaceWire. Compatible with PMC, PCI, PC104p versions of the SpaceWire design.
5/2011 Product Release PCIeBiSerialDb37-RTN8 Clientized version with 1mbyte+ receive buffer for 40 MHz byte wide data stream. 48K TX buffer with programmable TX rate. DMA support both functions. 8 bit data plus clock. LVDS IO. Please see the Dynamic Data Sheet and downloadable manual for more information. Windows® and Linux support.
4/2011 Product Release PMC-MC-X4 has been updated to add client requested features. The new additions include voltage monitor circuits which test the power supply voltages for high and low limits, thermal protection - the main power supply is shut down if the board level temperature reaches a programmable limit, a separate power supply for the fans to increase the power available to the PMC´s and to continue fan operation if the thermal limit is reached, optional vertical power entry, and a fused off board power connector to allow the local supplies to be used to support external devices. Now shipping.
3/2011 News Release Paul Kirpes has been promoted to Manufacturing Manager. Paul has his BS EE from Chico State University. Paul will bring his engineering expertise to our manufacturing group ensuring engineering level solutions for our manufacturing processes.
8/2010 Product Release Pc104pPWR28 & Pc104pPWR12 have been updated to be implemented on a common PCB "PC104pPWR" The updated design features PowerPak FET´s, larger inductors, higher current ratings and lower noise.
7/2010 Product Release IP-ConnectorSaver is a new design: used to allow for taller IP Modules, and to save wear on the built in connectors when high repetitions are used - for example in test. A small PCB is used to interconnect stacked IP Module connectors. The PCB is made as small as practical and does not impinge on the IP parts surface area.
6/2010 Product Update PC104p-BiSerial-III has been updated. Updated features include an additional FLASH device to allow for larger Xilinx FPGA through Spartan 3 4000, 2 additional PLL clock inputs, improved analog isolation, new switches for Differential IO with larger bandwidth and smaller impedance.
4/2010 Product Update PCIeBPMCX1 has been updated. The power supplies have been updated to handle more current under a wider temperature range. Revision 3+ boards can handle up to 9.5A on the 5V and 3.3V rails steady state in a lab environment without additional cooling. Please refer to the Dynamic Data Sheet for more information. The FET´s and planes have been updated to take advantage of new package options with better thermal characteristics with fantastic results. Extensive load testing has been performed to verify the design and characterize operation.
4/2010 Product Update IP-ReflectiveMemory has been updated to include new features. The updated revision B4 has added control bits to provide more user control over network restart. The standard automatic master node copy to the other nodes is the default with options to suppress the automatic update. An additional option to move all RAM writes to the network allows an alternate node to refresh the system with the data in the local RAM or for multiple nodes to each handle part of the refresh action under software control.
When an active network is disconnected to add another node or one of the equipment nodes has an issue of some sort, the network will automatically detect the down situation and the subsequent re-connection. When the network is restored the Master node can automatically refresh all nodes to make sure all match or the new features can be used to allow for software management of the restart. This is a FLASH only update and can be applied to all previously purchased cards [if desired].
1/2010 New Product Announcement PCIBPC104pET is an industrial temperature range PC104p carrier for PCI bus systems. Up to 4 active PC104p cards can be installed into the stack. Both front and rear can be used to allow options for stack growth within the chassis. The design is robust with extended temperature components, impedance controlled, PCI compliant routing, heavy power planes with decoupling for the PC104p voltages. and more. With the PCIBPC104pET ( PCI Bridge PC104p Extended Temperature) adapter / carrier converter card all you have to do is install your PC104p´s onto the adapter, and plug into the PCI slot. PCIBPC104pET is a universal voltage shorter than 1/2 length PCI card. The PC104p stack can be programed to use 3.3 or 5V for VIO. The bridge provides plug and play operation.
1/2010 Product Update Announcement PMC-BiSerial-III has a another "clientized" version available the "NASA1". The design features 4 channels used for telemetry. Each channel has a different function: LADEE-LLST, NMS, UART, Manchester (Uplink and Downlink). The transmit rate is selected with a PLL allowing for custom user frequencies. Interrupts, status and error checking. LVDS is used for LADEE and RS-485 for the other IO including a 14 bit parallel port.
More about PCIe-Spartan-VI: User programmable Spartan VI FPGA supported with 16 DMA ports, 40 Differential IO [LVDS and or RS-485], 12 TTL, 8 PLLs with 3 clock references each. Windows SW package includes User R/W functions to control the user design plus built in features with dedicated SW. The Bus FPGA handles the host interface and provides a General Purpose 32 bit 50 MHz bus to the User FPGA plus 8 channels with Rx and Tx lanes between the Bus and User FPGAs. The lanes are byte wide and have flow control built in. SW support for DMA operation to use with the User FPGA via the byte lanes. QSPI for User image. SW based JTAG load of User FPGA in next software release. Industrial temperature components. IO supported with D100 connector. Same pinout as PCIe-AlteraCycloneIV design. Reference VHDL project available for User FPGA.
Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
11/2024 Updated Driver and PCB Updated IO interface now uses FETs to allow up to 50V IO and up to 200 mA sink per transmit line. Each Input line now uses a series resistor and zener diode to allow a wide range - TTL - 50V on the input lines. The IP-Parallel-HV and IP-Parallel-HV-Test models have been combined. Addresses for the base model remain the same. Updated Win10 driver and reference SW package included with purchase. Test features added include controlling the second interrupt line, memory implemented in the memory space, and Address capture to support testing IP Module Carriers and developing drivers. The same PCB is utilized for IP-Parallel-HV-Miller [implements Miller encoding/decoding. Similar to Manchester], IP-HaveQuick[Time of Day receiver / transmitter utilizing HQT Manchester encoded data], and IP-Crypto[Interface with KYK-13 to read the key]. Use the manuals tab to navigate to the user manual for more detail.
10/2024 Updated Design PMC2PCI has been updated to support continued manufacture. Passive design with 32-64 bit operation depending on carrier installed into. 25-66 MHz clock rates, 5V and 3.3V keyed slots - actual PCI voltage determined by carrier. One slot available at a time. Install a PCI device into a PMC position. Right angle mounting available for parallel PCI and PMC installation.
09/2024 Updated SpaceWire Monitor with more memory and two added ports by Dynamic Engineering.. SpaceWire Monitor can be used to capture the communication between two SpaceWire nodes as well as provide two standard SpaceWire nodes with all of the features of our BK models. For the monitor ports, both sides are captured, filtered and stored to memory. Data is stored by packet and each packet is pre-pended with time, number and size. SpaceWire-Monitor can capture the data needed to do system / platform validation, debug tricky communications issues, capture HW data errors and more. Software currently executes with Linux and Windows®. SpaceWire-Monitor is a build option for PCI, PCIe, PMC, PC104p, and PCI-104 models of SpaceWire IO. All models offered have 32 MegaBytes of storage per port. DMA transfers data to the user specified file. NVMe or HDD with cache recommended for file storage. Data is stored as binary. Application includes binary conversion utility to provide human readable files. Click below for the SpaceWire-Monitor data page. Use the manuals tab to navigate to the user manual for more detail.
8/2024 Updated Design ccXMC-Serial has been updated with additional functionality. The new features include programmable active edge, CRC algorithm, clock count for HDLC and programmable clock burst for NRZ.. The base features include Spartan 6 FPGA, DDR, PLL, temperature sensor, 16 RS-485/LVDS transceivers, and 3 ports with programmable RS-232/RS-485 suitable for UARTs and similar. ccXMC-Serial is a conduction cooled XMC implementation. The IO is assigned to be compliant with SOSA requirements utilizing the Pn6 rear IO connector. The first design implemented on this platform is ccXMC-Serial-HDLC. 2 ports of HDLC, 2 ports of NRZL, and 3 ports of UART are implemented in this design. Windows drivers and reference SW currently available. HDLC and NRZL are supported with RS-485 transceivers.
7/2024 Updated Designs PMC-SpaceWire-BK, PCI-SpaceWire-BK , and PC104p-SpaceWire-BK PCBs and Linux packages have been updated. PMC-SpaceWire-BK, PCI-SpaceWire, and PC104p-SpaceWire join PCIe-SpaceWire-BK featuring enhanced DDR based memory with a default allocation or 32 Mbytes per port. The standard features are retained. PMC-SpaceWire-BK, PCIe-SpaceWire-BK as well as the other models implement SpaceWire [ECSS-E-ST-50-12C specification] in a convenient format. Four fully independent and highly programmable SpaceWire ports are provided by the SpaceWire-BK design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Rx ports autobaud. First character synchronization. The Win10/11 and Linux software packages support all of the features of the SpaceWire-BK design, and the UserAp reference software demonstrates the features including: internal and external loop-back with and without DMA operation. For example, several frequency files are provided and the UserAp software can automatically load them for you. Set any port to any programmable frequency. The Win10 and Linux packages are included with your purchase of SpaceWire-BK models. Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
5/2024 New Design PCIe-Spartan-VI is now available. User programmable Spartan VI FPGA supported with 16 DMA ports, 40 Differential IO [LVDS and or RS-485], 12 TTL, 8 PLLs with 3 clock references each. Windows SW package includes User R/W functions to control the user design plus built in features with dedicated SW. The Bus FPGA handles the host interface and provides a General Purpose 32 bit 50 MHz bus to the User FPGA plus 8 channels with Rx and Tx lanes between the Bus and User FPGAs. The lanes are byte wide and have flow control built in. SW support for DMA operation to use with the User FPGA via the byte lanes. QSPI for User image. SW based JTAG load of User FPGA in next software release. Industrial temperature components. IO supported with D100 connector. Same pinout as PCIe-AlteraCycloneIV design. Reference VHDL project available for User FPGA.
Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
5/2024 New Design ccXMC-Serial is now available. The base features include Spartan 6 FPGA, DDR, PLL, temperature sensor, 16 RS-485/LVDS transceivers, and 3 ports with programmable RS-232/RS-485 suitable for UARTs and similar. ccXMC-Serial is a conduction cooled XMC implementation. The IO is assigned to be compliant with SOSA utilizing the Pn6 rear IO connector. The first design implemented on this platform is ccXMC-Serial-HDLC. 2 ports of HDLC, 2 ports of NRZL, and 3 ports of UART are implemented in this design. Windows drivers and reference SW currently available. HDLC and NRZL are supported with RS-485 transceivers.
3/2024 Updated Design PCIe-SpaceWire-BK PCB and Windows package Has been updated. Now featuring enhanced DDR based memory with a default allocation or 32 Mbytes per port. The standard features are retained. PCIe-SpaceWire-BK as well as the other models implement SpaceWire [ECSS-E-ST-50-12C specification] in a convenient format. Four fully independent and highly programmable SpaceWire ports are provided by the SpaceWire-BK design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Rx ports autobaud. First character synchronization. The Win10/11 software package supports all of the features of the SpaceWire-BK design, and the UserAp reference software demonstrates the features including: internal and external loop-back with and without DMA operation. For example, several frequency files are provided and the UserAp software can automatically load them for you. Set any port to any programmable frequency. The Win10 package is included with your purchase of SpaceWire-BK models. Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package. Please see the Dynamic Data Sheet for links to HW and SW manuals plus detailed information.
2/2024 Updated Design PCIeBPMCX1 Has been updated. The bridge in use since 2007 went EOL and has been replaced with a Pericom PI7C9X130DNDE. The new bridge retains the 1-4 lane PCIe capability and provides the same options for 32/64 bits and 25-133 MHz. Please see the updated manual for settings and more detailed descriptions. In addition the 5V and 3.3V power supplies have been updated to provide up to 15A each. A new feature is an optional AP power connector with a standard 2x3 configuration to match PC internal power harnesses. The rear IO and bezel IO configurations are retained to provide a constant interface for cabling. The bridge is transparent and no SW changes required unless optimizing for high speed DMA operation. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
8/2023 Updated Design VPX-GLIB Has been updated to incorporate the PCIe interface to operate in parallel with the original SPI control path. VPX-GLIB is a multi-purpose hardware design supplying many system supervisor and space saving interfaces. VPX-GLIB is controlled via SPI bus [LVDS] using CLK, EN, SEL [2-0], MOSI, MISO. The SPI interface with the CPU is received and decoded. SPI accesses to internal functions are re-routed to a second decoder which extracts data to be written or packages data to be read. The extracted data is stored into a local register, and then parallel loaded to the target register. Accesses for SMB are re-routed to that interface. The PCie interface operates in parallel with the SPI interface - both affect the same register set allowing for either or both buses to be used for control. Base design provides LVDS, 485, single ended electrical interfaces with conversion, direction and termination control. Local voltage plus external voltage measurements with 3x LM81s, remote temperature measurement [TMP422] with automated HW interface, Multi-voltage inputs with programmable set-points. 10 MHz Clock reference testing and forwarding. Industrial Temperature range. Please see the Dynamic Data Sheet for links to HW manuals and detailed information. Win10 software package available to support access over the PCIe bus.
8/2023 New Design PCIe8LXMCX2HL A customized version of PCIe8LXMCX2. The rear IO options are optimized for the client requirement with the XMC rear IO broken out to 4 connectors per position. The interconnects are a combination of 50 ohm single ended and 150 ohm differential pairs. The differential signals are matched length. Base features common with PCIe8LXMCX2: Adapt 1 or 2 XMCs into a PCIe system. Gen1-3 compatible, Updated switch, clock distribution, incorporated Connector Bus, and power supplies. 8 lane connection to the PCIe bus with 8 PCIe lanes to each of the XMC positions. Options for FANs, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface.
8/2023 Updated Windows Package PCIeAlteraCycloneIV is now supported with Win10/11 drivers and reference SW. Driver and Hardware Manuals are available for download. Both drivers [Linux and Windows] are available to clients of PCIeAlteraCycloneIV along with reference software showing how to use the software to control the User design. Support package includes generic Read and Write operations to support user changes to the base memory map.
PCIeAlteraCycloneIV features Cyclone IV FPGA - 115, GPIO control bus plus 16 DMA channels to support user designs based on RS-485 and / or LVDS IO types. A Spartan 6 FPGA handles the traffic in and out of the PCIe bus and the user has access to the Cyclone IV. 40 differential pairs and 12 TTL IO are available to the user along with 24 PLLs.
07/2023 Updated ASCB interface for PCIe. Due to parts shortages ASCB has been redesigned to provide greater availability. ASCB is supported with two dual redundant ports utilizing the standard DB9 connector and pinout. D [Manchester] and Enhanced [8b10b] protocols supported. Dual Port RAM is used to store messages to transmit and data received from the ASCB interface. DMA is supported. In addition, a PMC position is supplied to support applications with need of local processing in the form of a PrPMC. Alternatively the PMC position can be used to add more IO to your system. Windows® SW package by Dynamic Engineering. Linux package by The Goebel Company.
06/2023 New SpaceWire Monitor Windows® SW package by Dynamic Engineering. SpaceWire Monitor can be used to capture the communication between two SpaceWire nodes. Both sides are captured, filtered and stored to memory. Data is stored by packet and each packet is pre-pended with time, number and size. SpaceWire-Monitor can capture the data needed to do system / platform validation, debug tricky communications issues, capture HW data errors and more. Software currently executes with Linux and Windows®. SpaceWire-Monitor is a build option for PCI, PCIe, PMC, PC104p, and PCI-104 models of SpaceWire IO. All models offered have 576 KBytes of storage per port. DMA transfers data to the user specified file. NVMe or HDD with cache recommended for file storage. Data is stored as binary. Application includes binary conversion utility to provide human readable files. Click below for the SpaceWire-Monitor data page. Use the manuals tab to navigate to the user manual for more detail.
4/2023 Linux Support Package for PMC-Parallel-485-NG1.
PMC-Parallel-485-NG1 provides register based GPIO plus 2 cascaded counters, fused 3.3V, received and redriven differential pair. The counters can be operated with a divided clock with external and internal sources. The counters can be used as interrupt generators. Total count or specific bits within the count can be selected. The base design has 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Linux package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485-NG1. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab. Windows and Linux currently supported.
2/2023 Win 10/11 Driver IP-1553 now features a Window® support package. The hardware includes a Spartan VI FPGA and HOLT 1553 interface. These updates provide Mil-STD-1553 support in an IndustryPack format. Industrial temperature components throughout. SW compatible with the previous versions. Win10 and Linux SW packages. Control all aspects of the single (-1) or two port (-2) models. Each port is dual redundant with header options for direct and transformer coupled operation. IP-1553 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
1/2023 Maxwell-2 Revision 02 released.
Maxwell-2 is a standalone micro computer with FPGA, Memory, CPU and IO. Spartan 6 [45 or 75] with QSPI FLASH to configure. Micro Blaze CPU built into the FPGA fabric allowing embedded Linux applications to run along with custom VHDL/Verilog implementations for your project. DDR, FRAM, FLASH, Ethernet, USB, Parallel Ports, LEDs, RTC with battery back-up, plus push button and dipswitches for user input. Internal power supplies only require a 5V external input. Multiple clock references supplied to FPGA and IO devices. Industrial Temperature components. Reference manual available on the Dynamic Data Sheet. See the Models tab.
12/2022 Win10/11 Support Package for PMC-Parallel-485-NG1.
PMC-Parallel-485-NG1 provides register based GPIO plus 2 cascaded counters, fused 3.3V, received and redriven differential pair. The counters can be operated with a divided clock with external and internal sources. The counters can be used as interrupt generators. Total count or specific bits within the count can be selected. The base design has 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485-NG1. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab. Linux for this model is scheduled.
08/2022 Win10 Support Package for PMC-Parallel-485.
Register based GPIO with options for bezel and rear panel IO. 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.11/22 Updated Design: PCIe8LXMCX2 Adapt 1 or 2 XMCs into a PCIe system with PCIe8LXMCX2. Now Gen1-3 compatible, Updated switch, clock distribution, incorporated Connector Bus, and power supplies. 8 lane connection to the PCIe bus with 8 PCIe lanes to each of the XMC positions. Connector Bus option creates a high speed inter-connect between the XMC rear IO connectors to support Signal Processing and other high bandwidth requirements. Isolation resistors are incorporated for almost zero stub length. Matched length for each option, impedance controlled, differential routing. Standard differential pair definitions. Options for Jn4, Jn6, FANs, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. A detailed selection map is available in the manual. See Dynamic Data Sheet for more information and manuals.
11/2022 New Version IP-Parallel-TTL-PATT features a 32 bit Pattern Generator plus 16 bit GPIO port [TTL / LVTTL interface]. 100 MHz reference along with user programmed divisors to supply COS and Pattern Generation references. Pattern Generator currently has 8 Types to choose from. The first option is User Data. Patterns written to the FIFO [4Kx32] are broadcast at the programmed rate. The remaining types utilize the built in controller to output the selected pattern. The limits [Start and Stop], Rate of Change [Slope], Number of cycles to output [Count], and Horizontal Count [HCount] are used to control the operation of Rising and Falling Ramps, Pyramids and inverted Pyramids, Square Wave, Shift Up, and Trapezoidal waveforms. Various status and optional interrupts are available to manage the interface. The recieve mode can be enabled to operate separately or in parallerl with the Pattern Generator. Data is captured on the rising edge of the reference clock and stored into the Rx FIFO [4Kx32]. Driver has Read and Write File operations for burst reads and writes when using the FIFOs.
In addition, a 16 bit GPIO parallel port with COS [change of state] capability is provided. Selectable Rising, Falling, Interrupt Enable, Polariity, Direction, Edge/Level controls to provide complete control over the interface. Win10/11 support. .
10/2022 New Version IP-Parallel-TTL-DPR provides a parallel interface to interconnect with a memory based system. A19-0, D15-0, READ, WRITE, ACK, BUSY supported. 100 MHz reference used to have precise timing. Simple structure to send commands to the interface to Write to memory, Read from memory and Read multiple from memory. Commands stored in 255 deep FIFO queue. 1Kx16 FIFO to store data from Read commands. In addition, an 8 bit GPIO parallel port with COS [change of state] capability is provided. Programmable sample rate for COS operation. Win10/11 support. Target simulator developed for test purposes. If your timing is different let us know know and we can modify to suit your requirements..
09/2022 Updated Model "ORN1" of ccPMC-BiSerial-VI.
2 ports with SDLC and 2 ports with NRZ/NRZL functions. Parallel port with mux control to select SDLC, NRZ/NRZL, or Parallel port operation. SDLC is Dual Port RAM based with programmable message length, interrupts etc. NRZ/NRZL is highly configurable with number of bits per transfer [packet descriptors], MSB/LSB first operation, Clock Sense, Data Sense, frequency of transmission, time between packets sent, time to wait for end of message, Programmable flags for Almost Full and Almost Empty FIFO. Interrupt or polled operation. 32 differential IO [485 or LVDS]. Temperature Sensor with state-machine to manage serial interface. PLL for custom frequencies. Industrial Temperature components. Rear IO (Pn4). Windows package supports all modes and comes with reference SW and test menu. VxWorks package - 6.9 supported. Linux package released. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.09/2022 Win10 Support Package for PMC-Parallel-485.
New Feature included in support package. Two new utilities are available on the UserAp menu: Print Registers and Modify Registers. Print Registers reads and prints the current contents of the registers within PMC-Parallel-485. Registers supported with structures have the settings displayed showing the current values of the structure. Modify Registers allows the user to change the settings on the board without writing software. Quick start options to program to transmit or receive. Toggle option to have a register change between two values via single key stroke. Great for initial familiarization and to use PMC-Parallel-485 as a tool to interact with other hardware. The rest of the files within UserAp provide a great references for initialization - connecting with the driver, performing IO tests, using interrupts, and more.PMC-Parallel-485 provides register based GPIO with options for bezel and rear panel IO. 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.
08/2022 Win10 Support Package for PMC-Parallel-485.
Register based GPIO with options for bezel and rear panel IO. 32 + 2 RS-485/RS-422 or LVDS. Programmable Tx/Rx and termination. Programmable interrupt / polled IO with rising, falling, level, inversion options per bit. Separate mask to allow combination of polled and interrupt driven IO. 2 additional IO at bezel for external clock and clock enable. Industrial Temperature components. Windows package supports all modes and comes with reference SW and test menu - included with purchase of PMC-Parallel-485. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.08/2022 New Model "ORN1" of ccPMC-BiSerial-VI.
2 ports with SDLC and 2 ports with NRZ/NRZL functions. Parallel port with mux control to select SDLC, NRZ/NRZL, or Parallel port operation. SDLC is Dual Port RAM based with programmable message length, interrupts etc. NRZ/NRZL is highly configurable with number of bits per transfer [packet descriptors], MSB/LSB first operation, Clock Sense, Data Sense, frequency of transmission, time between packets sent, time to wait for end of message, Programmable flags for Almost Full and Almost Empty FIFO. Interrupt or polled operation. 32 differential IO [485 or LVDS]. Temperature Sensor with state-machine to manage serial interface. PLL for custom frequencies. Industrial Temperature components. Rear IO (Pn4). Windows package supports all modes and comes with reference SW and test menu. VxWorks is released - 6.9 supported. Linux in process. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.5/2022 New Version: PCIe4LHOTLinkx5-SMB HOTLink is used in applications demanding high speed and high reliability including photography, sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. PCIe4LHOTLinkx5 is a PCI Express device. The -SMB version has a single channel with Tx and Rx ports utilizing the SMB connectors. The HOTLink ports are supported with separate DMA transfer engines plus local memory. Full duplex operation with 256Kbytes of FIFO memory per port. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames. Win10 driver and reference application available. See Dynamic Data Sheet for more information and manuals.
05/2022 PMC-OctalUART-232 Win10 - Dynamic Engineering has updated the software package for PMC-OctalUART-232 with Windows 10 support. The SW package is included with your purchase of PMC-OctalUART-232. Drivers and UserAp reference package with examples for set-up [baud rate, word size, stop bits, RTS/CTS etc.], Transmitting and Receiving characters. Internal and External loop-back examples. External tests with and without flow control in use. Driver includes IOCTLs for write multiple and read multiple. Signals [RX, TX, RTS, CTS, DTR, DSR per port]. Eight ports per device. ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Rear IO model shown below.
04/2022 IP-QuadUART-485 Win10 - Dynamic Engineering has updated the software package for IP-QuadUART-485 with Windows 10 support. The SW package is included with your purchase of IP-QuadUART-485. Drivers and UserAp reference package with examples for set-up [baud rate, word size, stop bits, RTS/CTS etc.], Selection of Full or half duplex RS-485 operation, Transmitting and Receiving characters. Internal and External loop-back examples. External tests with and without flow control in use. Driver includes IOCTLs for write multiple and read multiple. 485 signals [RX, TX, RTS, CTS, DTR, DSR per port]. Four ports per device. Designed to work with Dynamic Engineering IP Carrier group driver package. ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
04/2022 IP-QuadUART Win10 - Dynamic Engineering has updated the software package for IP-QuadUART with Windows 10 support. The SW package is included with your purchase of IP-QuadUART. Drivers and UserAp reference package with examples for set-up [baud rate, word size, stop bits, RTS/CTS etc.], Selection of RS-232 or RS-485 operation, Transmitting and Receiving characters. Internal and External loop-back examples. External tests with and without flow control in use. Driver includes IOCTLs for write multiple and read multiple. 485 signals [RX, TX, RTS, CTS per port] 232 signals[Rx, Tx, RTS, CTS, DTR, DSR, RI, CD per port]. Four ports per device. Designed to work with Dynamic Engineering IP Carrier group driver package. ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
04/2022 PC104p-SpaceWire updated - Dynamic Engineering has updated PC104p-SpaceWire to support the BK and SpaceWire Monitor models. Purchase includes Win10 and Linux SW support. 4 ports each separately programmable to operate up to 200 MHz. DMA engine for each port / direction [8 total]. Time code included. Standard MDM connectors. RMAP with separate Linux package. Industrial temperature components standard. Options for added memory [see -128 models], ROHS or standard processing. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
03/2022 VPX2IP updated - Dynamic Engineering has updated VPX2IP to have Win10 support along with more clocking options and VHDCI connectors at the bezel / front panel. VPX2IP is a 3U 4HP mechanical configuration with two IP Module locations. Front Panel IO is standard utilizing two 68 position VHDCI connectors at the VPX bezel. Compatible with standard VHDCI cable. VHDCIterm68 can be used as a breakout. Rear Panel IO is also available with IP module IO routed to the VPX rear connector [P2/J2]. Multi-word transfers are supported: 64, 32, 16, and 8 bit transfers are easy to implement with standard CPUs. VPX2IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range components, Independent 8 and 32 MHz IP Module operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. PCIe single lane operation. Windows, Linux, and VxWorks drivers and reference software. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
12/2021 Option for alternate pinout of PMC-BiSerial-VI-UART.
The -LM12 option selects an alternate FLASH installation with pinouts matching the Abaco / Radstone PMC-Q1F design. PMC-BiSerial-VI-UART-LM12 features the same design just rearranged. The extra features from the standard -UART design are pushed onto unused pins. 8 UART I/O ports each consisting of RS-485 transmit and receive data. [LVDS is an ordering option] The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the port reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Alternate reference frequencies are available. Reference clock for each port is selectable between the 32 MHz reference and a user programmed PLL frequency. Each UART port has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFOs. DMA support on all channels. 5 modes can be selected per fully independent node: Standard UART (unpacked), Packed, Packetized, Alternate Packetized, and Test. Options for Bezel and Rear IO.
Windows and Linux packages support all modes and comes with reference SW. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.12/2021 Updated SpaceWire Software Release Dynamic Engineering has released revision 1p5 of the Windows 10 support package for SpaceWire-BK models. All types including curent releases of PMC, PCI, PCI-104, PCIe can use the updated package.
PCIe-SpaceWire-BK as well as the other models implement SpaceWire [ECSS-E-ST-50-12C specification] in a convenient format. Four fully independent and highly programmable SpaceWire ports are provided by the SpaceWire-BK design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Rx ports autobaud. First character synchronization. The Win10 software package supports all of the features of the SpaceWire-BK design, and the UserAp reference software demonstrates the features including: internal and external loop-back with and without DMA operation. For example, several frequency files are provided and the UserAp software can automatically load them for you. Set any port to any programmable frequency. The Win10 package is included with your purchase of SpaceWire-BK models. Please contact Dynamic Engineering (sales@dyneng.com) for a link to the software package.
11/2021 New Design cPCIBPMC3U32.
3U 4HP cPCI adapter for PMC. Transparent bridged model with 5V / 3.3V compatible PCI interface on primary side and selctable voltage on secondary [PMC] side of bridge. 32 bit plug and play PCI operation. 33/66 MHz primary. Up to the primary frequency for secondary clock. PMC IO through the bezel. Option for rear IO using Pn4/Jn4 routed to cPCI J2. Matched length, impedance controlled [100 ohm differential] for rear IO. Local filtering on 3.3V and 5V power rails with full current mini-planes to power the PMC. +/- 12V also supplied with 1A+ traces. Industrial temperature. Fan option. ROHS option. Conformal Coating option. Isolate by voltage or clock rate. PCI trace lengths are within specification. Reference manual available on the Dynamic Data Sheet. See the Manuals tab.11/2021 New Design GPIO model of ccPMC-BiSerial-VI.
32 differential IO [485 or LVDS]. Each IO is independent with programming options for Edge or Level, COS (Change of State), Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Rear IO (Pn4). Windows package supports all modes and comes with reference SW and test menu. Linux scheduled. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.10/2021 New Design cPCI3U32B1LPCIeX4. Converts the PCI bus used in cPCI to PCIe to allow use of PCIe modules in a cPCI system. 3.3V and 5V tolerant PCI bus with reverse bridge to create 1 lane PCIe interface. 4 lane connector provided to allow for multiple cable and interface options on the PCIe side. Local high stability 100 MHz generation with shunt to select Spread [SSC] or fixed clock [NSSC] operation. Industrial Temperature components. Support for 4 GPIO, EEPROM, External 12V for designs requiring additional current. 3U 4HP implementation. Transparent bridge does not require programming.
10/2021 Updated Design Parallel-TTL-GPIO Win10 Package. Available in XMC and PMC formats. 64 single ended IO with software programmable voltage reference [3.3V or 5V]. Each IO is independent with programming options for Edge or Level, COS, Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Bezel IO with VHDCI connector and / or Rear IO from (PMC)Pn4, (XMC) Pn4 and/or Pn6
Win10 & Linux support packages. Driver and reference software set [UserAp]. See models tab for manual download - HW and SW.
10/2021 Windows 10 package for UART model of PMC-BiSerial-VI.
8 UART I/O ports each consisting of RS-485 transmit and receive data. [LVDS is an ordering option] The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the port reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Alternate reference frequencies are available. Reference clock for each port is selectable between the 32 MHz reference and a user programmed PLL frequency. Each UART port has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFOs. DMA support on all channels. 5 modes can be selected per fully independent node: Standard UART (unpacked), Packed, Packetized, Alternate Packetized, and Test. Options for Bezel and Rear IO.
Windows package supports all modes and comes with reference SW and test menu. Reference HW and SW manuals available on the Dynamic Data Sheet. See the Models tab.09/2021 Updated Linux package for UART model of PMC-BiSerial-VI.
8 UART I/O ports each consisting of RS-485 transmit and receive data. [LVDS is an ordering option] The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the port reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Alternate reference frequencies are available. Reference clock for each port is selectable between the 32 MHz reference and a user programmed PLL frequency. Each UART port has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFOs. DMA support on all channels. 5 modes can be selected per fully independent node: Standard UART (unpacked), Packed, Packetized, Alternate Packetized, and Test. Options for Bezel and Rear IO.Linux package supports all modes and comes with reference SW and test menu. Compatible with current kernels.
09/2021 Updated RTN10 model of PCI-ECL-II.
Custom Parallel interface. 8 bit parallel data path [NECL input and output] with reference clock and enable. Data valid on programmable edge of clock, enable active high. Programable use of enable. DMA support, 12 bits uncommitted TTL IO. Updated with higher performance memory operation, increased FIFO size, added status, and operational enhancements. Improved DMA performance and new Linux driver with this release. 07/2021 New SpaceWire Monitor package by Dynamic Engineering. SpaceWire Monitor can be used to capture the communication between two SpaceWire nodes. Both sides are captured, filtered and stored to memory. Data is stored by packet and each packet is pre-pended with time, number and size. SpaceWire-Monitor can capture the data needed to do system / platform validation, debug tricky communications issues, capture HW data errors and more. Software is written in C and currently executes on Linux. The Monitor package is designed to utilize the latest Linux SpaceWire release [1.1.4]. SpaceWire-Monitor is a build option for PCI, PCIe, PMC, PC104p, and PCI-104 models of SpaceWire IO. All models offered have 576 KBytes of storage per port. DMA transfers data to the user specified file. NVMe or HDD with cache recommended for file storage. Data is stored as binary. Application includes binary conversion utility to provide human readable files. Click below for the SpaceWire-Monitor data page. Use the manuals tab to navigate to the user manual for more detail.
7/2021 Updated Design Parallel-TTL-GPIO Linux Package. Available in XMC and PMC formats. 64 single ended IO with software programmable voltage reference [3.3V or 5V]. Each IO is independent with programming options for Edge or Level, COS, Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Bezel IO with VHDCI connector and / or Rear IO from (PMC)Pn4, (XMC) Pn4 and/or Pn6
Win10 & Linux support packages. Driver and reference software set [UserAp]. See models tab for manual download - HW and SW.
06/2021 New RMAP SpaceWire Linux software package by Dynamic Engineering. SpaceWire Remote Memory Access Protocol (RMAP) was developed to support reading and writing from/to memory in a remote SpaceWire.node. RMAP can be used to configure a SpaceWire network, control SpaceWire nodes, and transfer data between nodes. Software is written in C and currently executes on Linux. The RMAP package is designed to utilize the latest Linux SpaceWire release [1.1.4] and can be modified to work with other third party SW packages and other companies HW. Click below for the SpaceWire summary page. Use the manuals tab to navigate to the user manual for more detail.
06/2021 Updated SpaceWire Linux Driver and Reference SW by Dynamic Engineering. The new release features enhanced interrupt processing for multi-port DMA operation and modifications to support the RMAP Linux package. The driver has been validated on the P2020 platform (multi-core PPC) which is big endian and i7 for little endian operation. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Win10 and VxWorks also available.
6/2021 Solar Power Dynamic Engineering is pleased to announce that we have added approximately 54 KW of solar power generation to our location. With the addition of the solar panels Dynamic Engineering will be better than net 0 on an annual basis. Dynamic Engineering contracted with Just Leaks for the installation of the system. 133 panels with almost 3000 square feet of collection. Dual sided panels to take advantage of the reflected energy on a commercial reflective roof. Special rack mounts with hinges to allow for future maintenance on the roof without removing the panels. Three phase power generation to allow future connection with storage devices to support our Manufacturing and Engineering requirements.
5/2021 Updated Design: PCIe8LXMCX1 Adapt an XMC into a PCIe system with PCIe8LXMCX1. 8 PCIe lanes routed to the XMC. Matched length controlled impedance traces suitable for Gen1-3. Options for FANs, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Updated with more current on the 5V and 3.3V supplies - with Rev 06 increased to 15A. Industrial Temperature components throughout. Power supplies allow user selection of delayed, immediate, and disabled for the +5V and +3.3V internal power supplies. If your XMC does not use one of the rails your inrush requirement can be reduced by disabling the unused supply. If your system has slow to program devices you will want the immediate turn on setting, and if your device is faster to load you can space out the inrush of the local supplies with the delayed setting. See Dynamic Data Sheet for more information and manuals.
3/2021 New Design cPCIBXMC3U32. Use your XMC in a cPCI environment. 3U 4HP adapter / carrier/ transition from cPCI to XMC standards. cPCIBXMC3U32 incorporates a 32 bit PCI interface [66 MHz capable, universal voltage] and converts to a single lane PCIe interface for the installed XMC device. The bridge is transparent - no SW development to use the adapter. XMC bezel aligns with cPCI bezel. XMC rear IO available with PMC style, XMC style or both connectors via cPCI J2. Industrial Temperature components. More information user manual available on Dynamic Data Sheet.
3/2021 Updated Designs PCI3IP, and PCI5IP - Added Features including VPWR plus upgraded to Spartan VI. PCI3IP features 3 IndustryPack Module positions in a half length PCI format design [Rev 11 and later]. PCI5IP incorporates 5 IP locations in a full length PCI format design [Rev 08 and later]. Both utilize industrial temperature devices. PCI3IP has been in production since 1999. PCI5IP since 2002. Through Dynamic Engineering´s continuous improvement plan the devices are still in production and serving our clients. If your system is PCI limited try the PCIe3IP and PCIe5IP models with similar features.
VPWR is the new name for the 5V rail supplied to the installed IndustryPack modules. 5V is the default to accomodate current designs. When the pin known as Reserved 1 [Pin 36] is grounded by one or more of the installed IP modules VPWR is switched to 3.3V as well as the reference to the terminations. Current FPGAs generally are not 5V tolerant plus require 3.3V for operation. The use of VPWR can save level translators and regulators on the IP Module.
Both of the updated designs are compatible with the unified DynEngIpCarrier driver, and DynEngIpCarrierAp. Driver and hardware support auto loading of IP Module drivers, access to each IP control register [carrier FPGA to control clock rate, interrupts, byte swapping, bus error, 32 bit conversion control etc.], Carrier registers for switch, revision, LEDs, interrupt status, etc. Full access to each of the IP address spaces [ID, IO, INT, MEM]. Reference Application provides examples of communicating with an IP in all address spaces, plus interrupts and handling bus errors. The reference SW for the carrier uses IP-Test as the target [modified IP-Parallel-HV]. IP Modules with Win10 driver packages have support specific to that module. Supported modules are auto-loaded. When an IP without a support package is detected IP-Generic is installed allowing use of third party IPs with the DynEngIpCarrier driver on a Dynamic Engineering IP Carrier.
3/2021 Updated Driver and Reference SW IP-Parallel-IO Win10 SoftWare package. The 7 standard models of IP-Parallel-IO [-TTL, -1, -2, -3, -4, -5, -485] are now supported with a unified Windows 10 reference software package. With this release all 7 models are covered. Revision 03 and 04 PCBs are compatible [Spartan II and Spartan 6 based designs]. The new unified driver package is compatible with the DynEngIpCarrier driver package. The new unified IpParIoUserAp has routines to demonstrate the use of the two counter timers, configuring and using the IO. Use of interrupts to manage the received IO and counter timers is included. Programming of the output waverform option is also included. The reference menu auto detects the type of IP installed and displays along with the details of that model. Carrier frequency of operation selection is demonstrated in the ATP Menu Item. The IOCTLs are grouped by _IO_ for common calls that apply to all 7 models, _N_ for calls specific to a particular model. The IOCTL is the same in all cases. The driver uses a common structure to communicate with the User program and auto alligns to the installed HW. A great reference to get you started. Included with your purchase of the IP-Parallel-IO family. HW and SW manuals available on the Dynamic Data Sheet - See link above or click on the photo.
2/2021 New Design Parallel-TTL-GPIO. Available in XMC and PMC formats. 64 single ended IO with software programmable voltage reference [3.3V or 5V]. Each IO is independent with programming options for Edge or Level, COS, Interrupt, Polarity. Programmable PLL plus on-board oscillator with secondary divider to supply COS reference frequency. Temperature Sensor with state-machine to manage serial interface. Industrial Temperature components. Bezel IO with VHDCI connector and / or Rear IO from (PMC)Pn4, (XMC) Pn4 and/or Pn6
Win10 support with Driver and reference software set [UserAp]. See models tab for manual download - HW and SW. Linux in development.
1/2021 Updated Design PMC-BiSerial-VI-HW1 is the ported and upgraded version of PMC-BiSerial-III-HW1. The updated version incorporates a Spartan VI FPGA, and industrial temperature components. These updates will allow for continued operation for years to come. SW compatible with the previous versions. Win10 and Linux SW packages. Linux available, Win10 in process. PMC-BiSerial-VI has 34 independent differential IO. Each of the IO have programmable termination, and direction controls. The IO is available for system connection through the front panel SCSI connector and / or Pn4. SCSI Cable and HDEterm68 can be used as a breakout for the IO.
The HW1 protocol implemented provides 32 Manchester encoded data ports per PMC-BiSerial-VI. Each port can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 channels. The 32 port plus 2 additional IO can be used for a parallel port. Bit level programmable for function, Direction, Termination. Option to use I2O or standard interrupts. The reference frequencies can be derived from the on-board oscillator or SW programmable PLL. The pin definitions are consistent with the PMC-BiSerial-III-HW1 design to allow migration to the PMC-BiSerial-VI-HW1 quickly and easily.
1/2021 Updated Driver and Reference SW For use with IP-HaveQuick- Win10 SoftWare package. IP-HaveQuick supports both Transmission and Reception of HaveQuick data. HaveQuick is a Time of Day interface. The 1PPS sync pulse is followed by manchester encoded data with the data and time. New with this release is a control bit that allows the user to select standard [Msb] and Lsb First operation. The ones, and synchronization pattern are not affected by the selection. The payload data and parity are reversed on a byte basis when selected. The Win10 package includes demonstrations of setting up the transmitter with the current data and time as well as receiving data via register reads or using the FIFO storage. Interrupt and polled operation supported and demonstrated. The new driver package is compatible with the DynEngIpCarrier driver package. A great reference to get you started. Included with your purchase of IP-PAR-HQT
1/2021 Facilities Improvement Dynamic Engineering has contracted to add approximately 54 KW of solar power to our electrical system. 3 phase system using 133 panels. Expected to be on-line in time for summer. The roof was recently redone to improve drainage and insulation value with a highly reflective surface. The Bifacial panels use the direct energy from the sun plus the reflected energy from the roof to generate electricity.
12/2020 Updated Driver and Reference SW For use with IP-Parallel-IO- Win10 SoftWare package. An integration effort is underway with the 7 standard models of IP-Parallel-IO [-TTL, -1, -2, -3, -4, -5, -485] to create a unified Win10 driver package. With this release the TTL and 485 models are covered. Revision 03 and 04 PCBs are compatible [Spartan II and Spartan 6 based designs]. The new unified driver package is compatible with the DynEngIpCarrier driver package. The new unified IpParIoUserAp has routines to demonstrate the use of the two counter timers, configuring and using the IO. Use of interrupts to manage the received IO and counter timers is included. The reference menu auto detects the type of IP installed. Frequency switching is demonstrated in the ATP option. The IOCTLs are grouped by _IO_ for common calls that apply to all 7 models, _485_ for calls specific to the -485 and _TTL_ for the TTL specific calls. A great reference to get you started. Included with your purchase of the IP-Parallel-IO family
10/2020 Updated Driver and Reference SW For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP - Win10 SoftWare package. An integration effort is underway with the 4 models [PCI5IP, PCI3IP, PCIe5IP, PCIe3IP] now covered by the unified DynEngIpCarrier driver, and DynEngIpCarrierAp. cPCI and PC104p models will be added. Driver supports auto loading of IP Module drivers, access to each IP control register [in carrier FPGA to control clock rate, interrupts, byte swapping, bus error, 32 bit conversion control etc.], Carrier registers for switch, revision, LEDs, interrupt status, etc. Full access to each of the IP address spaces [ID, IO, INT, MEM]. Reference Application provides examples of communicating with an IP in all address spaces, plus interrupts and handling bus errors. The reference SW for the carrier uses IP-Test as the target [modified IP-Parallel-HV]. IP Modules with Win10 driver packages have support specific to that module. Supported modules are auto-loaded. When an IP without a support package is detected IP-Generic is installed allowing use of third party IPs with the DynEngIpCarrier driver on a Dynamic Engineering IP Carrier.
7/2020 New Product Announcement: PCIe-Harpoon
PCIe-Harpoon can be used for simulation, control, command and other embedded IO functions. The
Harpoonis being used for similation in its first applicaion. The client is using the Harpoon to simulate part of their system to allow testing of the rest of their system. The design has 4 channels to allow testing of multiple target hardware sets in parallel. Each channel has opto-isolated inputs set-up for 28V, High Side switches utilizing opto-coupled FETs with 60V 1.5A max per switch, Low Side switches also with opto-coupled FETs, 115V detection, and differential IO. The differential IO is configured to command and respond to the system under test. PCIe-Harpoon has a large FPGA to allow for customerized versions in new applications. Win10 driver and application software available. Cables and breakout [terminal strip] adapters also available.
Available now.
6/2020 Linux Driver IP-1553 now features a Linux support package. The hardware includes a Spartan VI FPGA and HOLT 1553 interface. These updates provide Mil-STD-1553 support in an IndustryPack format. Industrial temperature components throughout. SW compatible with the previous versions. Win10 and Linux SW packages. Control all aspects of the single (-1) or two port (-2) models. Each port is dual redundant with header options for direct and transformer coupled operation. IP-1553 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
6/2020 IP-BiSerial-VI-GPIO - New model of IP-BiSerial-VI released. The GPIO model features 24 differential IO configured as a parallel port. Each bit is programmable to be an input or an output. Polarity, Termination, Edge/Level interrupt triggering with separate Rising and Falling edge enables. Interrupt or polled operation. Direct and filtered data ports. User programmable PLL or local oscillator selection for COS reference. 485 and LVDS IO. Windows 10 and Linux support - see Dynamic Engineering IP carriers
[ PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PCI-104, VPX2IP]. Industrial temperature standard.
IP-BiSerial-VI base features include: 24 independent differential IO each with programmable direction and termination. LVDS, RS485, and mixed IO types. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. 8 and 32 MHz IP Module operation. Use this IndustryPack module to implement Manchester, Miller, Serial and Parallel IO, telemetry, communications, command and control etc. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
3/2020 Updated Design PMC-BiSerial-6T20 has been upgraded to incorporate a Spartan VI FPGA, and industrial temperature components. These updates will allow for continued operation for years to come. SW compatible with the previous versions. Win10 SW package. PMC-BiSerial-6T20 has 20 independent transformer coupled IO plus 2 direct connection differential IO. Each of the transformer coupled IO have resistive and capacitive coupling with SW control. The discretes have the resistive termination. The IO is available for system connection through the front panel SCSI connector. SCSI Cable and HDEterm68 can be used as a breakout for the IO. The pin definitions are consistent with the PMC-BiSerial-3T20 design to allow migration to the PMC-BiSerial-6T20 quickly and easily.
3/2020 Updated Design XMC-Parallel-TTL has been upgraded to incorporate a Spartan VI FPGA and VHDCI interface. These updates will allow for continued operation for years to come. Industrial temperature components throughout. SW compatible with the previous versions. Win10 SW package. XMC-Parallel-TTL has 64 independent digital IO. The high density makes efficient use of precious XMC slot resources. The IO is available for system connection both through the front panel and via the rear [Pn4, Pn6] connectors. A high density 68 pin VHDCI front panel connector provides the front panel IO. HDEterm68 can be used as a breakout for the front or rear panel IO. The pin definitions are consistent with the PMC-Parallel-IO design to allow migration to the XMC-Parallel-TTL quickly and easily.
3/2020 New Design IP-Relay16 has been designed to support previous clients of the Systran IP-Relay16 design. 16 Form C relays. The relays are controlled by the host by setting or clearing bits in the Relay Control register. Each bit corresponds to one relay. When set the relay is energized. When cleared the relay is returned to the default state. Back EMF protection is provided on the control side of the relay. The voltage rating on each relay is up to 220 VDC, 250 VAC and 60W or 62.5 VA. The IP IO connector is limited to about 1 A per pin. The traces on the IP are rated for 1.5A. Industrial temperature components throughout. SW compatible with the previous versions. Win10 SW package. IP-Relay16 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
03/2020 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated VxWorks Driver for Versions 6.9 and 7. The driver has been validated on the P2020 platform (multi-core PPC) which is big endian. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 and Linux also available.
2/2020 Updated Design IP-1553 has been upgraded to incorporate a Spartan VI FPGA and HOLT 1553 interface. These updates will allow for Mil-STD-1553 support in an IndustryPack format for years to come. Industrial temperature components throughout. SW compatible with the previous versions. Win10 SW package. Control all aspects of the single (-1) or two port (-2) models. Each port is dual redundant with header options for direct and transformer coupled operation. IP-1553 Windows module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
1/2020 Updated Driver package for KAON1 interface released - TTL and HOTLink interfaces with command / response type interaction. 2 Ports per ccPMC-HOTLink-KAON1. A new Win10 driver and reference software package has been developed. Linux also available.
The main purpose is to provide an interface to allow a PC or other computer to communicate directly with KAON1 interface. The KAON1 interface is bidirectional and utilizes both TTL and HOTLink serial interfaces. Each side is supported with large FIFOs. "Channelized DMA"™ on TX and RX. PLL support for custom frequencies. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information.
12/2019 Updated Hardware Release Dynamic Engineering has released an updated model - PCIe-SpaceWire. The PCIe-SpaceWire internal PCI bus now operates at 50 MHz for a 50% gain in bandwidth. The increase in BW means more ports can operate at higher frequencies with greater loading.
PCIe-SpaceWire implements SpaceWire [ECSS-E-ST-50-12C specification] in a convenient PCIe format. Four fully independent and highly programmable SpaceWire ports are provided by the PCIe-SpaceWire design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. PCIe-SpaceWire provides a bridge from PCIe ⇔ SpaceWire. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
12/2019 IP-BiSerial-VI-BA27 - Update to BA27 model with more programmability. Added features include PDD = Pre Data Delay - a programmable delay from external trigger or SW enable to start transmitting, IWG = Inter Word Gap = a programmable delay between transmitted data, MultiCycle - operation with multiple words transmitted based on FIFO status. SingleCycle mode retained. 16,17,32,34 bit transfers. Msb/Lsb first operation. Programmable frequency. 485 and LVDS IO. Windows 10 and Linux support - see Dynamic Engineering IP carriers
PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PCI-104, VPX2IP]. Industrial temperature standard.
IP-BiSerial-VI base features include: 24 independent differential IO each with programmable direction and termination. LVDS, RS485, and mixed IO types. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. 8 and 32 MHz IP Module operation. Use this IndustryPack module to implement Manchester, Miller, Serial and Parallel IO, telemetry, communications, command and control etc. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
11/2019 Updated Driver package for ARC-210 interface released PCIe-BiSerial-DB37-LM9 supports communications with ARC-210 radios. A new Win10 driver and reference software package has been developed. Linux also available.
The main purpose is to provide an interface to allow a PC or other computer to communicate directly with an ARC-210 radio. The ARC-210 interface is bidirectional and is fully independent for Tx and Rx. Each side is supported with 4Kx32 Data FIFO plus 2Kx32 Packet FIFO. The transmitter "SendTiming" signal can be set to output the reference clock to allow for loop-back and alternate purpose uses. Interrupt or polled operation. "Channelized DMA"™ on TX and RX. 12 bit GPIO port [termination, direction independent on each bit]. RS-485 IO. TX in transmit SendTiming mode supported with PLL for user frequency. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information. This design can be ported to our other BiSerial formats - PMC, PCI-104 etc. Please contact Dynamic Engineering for these options.
11/2019 IP-BiSerial-VI-USR - user configurable / programmable FPGA based IP Module with 24 differential IO. Reference design [VHDL] available. On board FLASH to store the FPGA image for "instant on" operation. Windows and Linux support - see Dynamic Engineering IP carriers [PCI, PCIe, cPCI, PCI-104, VPX]. Industrial temperature standard. Spartan 6 LX25 device with block RAM and clocking elements to complete your design.
24 independent differential IO each with programmable direction and termination. LVDS, RS485, and mixed IO types. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. 8 and 32 MHz IP Module operation. Use this IndustryPack module to implement Manchester, Miller, Serial and Parallel IO, telemetry, communications, command and control etc. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Check the non-USR list - we may have your interface already imlemented.
9/2019 PMC2mPCI released PMC2mPCI is an adpater to convert between mPCI type III and PMC. It is a passive design with no additional SW required. Matched length, impedance controlled PCI bus with filtering. Mounts to any standard PMC location. Comes with mounting hardware. mini-PCI type III cards can add wireless and other interfaces to your PMC based project.
9/2019 Renewed Product Dynamic Engineering now has SCSI Cable. After being frustrated trying to find proper cables to support our clients we have decided to make SCSI cables a stocked item. 3Ft, 6Ft, 9Ft lengths with Latch -Block [clip] and Thumbscrew [screw] terminations available. Suitable for operation with PMC-BiSerial-VI and other embedded electronics using the SCSI connector. See HDEterm68 for a SCSI compatible screw terminal breakout.
9/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated VxWorks Driver for Versions 6.9 and 7. The driver has been validated on the P2020 platform (multi-core PPC) which is big endian. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 and Linux also available.
8/2019 PMC-BiSerial-VI-OSEH released PMC-BiSerial-VI-OSEH is an updated version of the original PMC-BiSerial-III-OSEH design. PMC-BiSerial-VI-OSEH is supported with a Win10 driver and reference software. Linux and VxWorks available by special request. OSEH is a 32 bit serial transfer with a gated clock reference. Data is transmitted until the local FIFO is empty. The design supports internal and external Tx clock references. The internal rate is set by the PLL - SW controlled. Programmable transmit rate, multiple interrupt options, programmable FIFO level, internal loop-back and more. 132Kx32 FIFO for transmit and receive ports. Independent DMA for Tx and Rx functions. RS485 based with LVDS as an option. The base design comes with bezel IO. Rear [Pn4] IO is an option. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information.
8/2019 Updated SoftWare Release Dynamic Engineering has released Win10 support for the BK models of SpaceWire. Covered are PMC-SpaceWire-BK, PCI-SpaceWire-BK , PCIe-SpaceWire-BK models in the standard, -128 and -128RX configurations. The support package comes with the Win10 signed driver and reference SW. The reference software provides examples of how to use, and how to test the SpaceWire devices including the use of DMA, programming the PLL, transmitting and receiving embedded data or files. A Quick Start User guide is now available with information about the included menu´s and in particular how to send or receive files using the menu. No user SW required.
The Dynamic Engineering SpaceWire family implements SpaceWire [ECSS-E-ST-50-12C specification] in a series of convenient formats. Four fully independent and highly programmable SpaceWire ports are provided. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
8/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated VxWorks Driver for Version 7. The driver has been validated on VxWorks-7 SR0540 SMP on the P2020 platform (multi-core PPC) which is big endian. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 andLinux also available.
8/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated Linux Driver [1.2]. The driver has been validated on an i7 Ubuntu server running 3.8.0-42 kernel (64 bit) SMP, Ubuntu server running 4.18.0-25 kernel (64 bit) SMP, and P2020 (32 micro-controller) running 2.6.35 (32 bit) SMP. All 6 models of SpaceWire [K std, K-128, K-128RX, BK std, BK-128, BK-128RX] have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous. Win10 and VxWorks also available.
7/2019 New SoftWare Release Dynamic Engineering has released Win10 support for the BK models of SpaceWire. Covered are PMC-SpaceWire-BK, PCI-SpaceWire-BK , PCIe-SpaceWire-BK models in the standard, -128 and -128RX configurations. The support package comes with the Win10 signed driver and reference SW. The reference software provides examples of how to use and how to test the SpaceWire devices including the use of DMA, programming the PLL, transmitting and receiving embedded data or files. The Dynamic Engineering SpaceWire family implements SpaceWire [ECSS-E-ST-50-12C specification] in a series of convenient formats. Four fully independent and highly programmable SpaceWire ports are provided. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
7/2019 New HW Release VPX-3U-COOL joins VPX-6U-COOL to provide cooling to VPX 3U hardware. Up to 6 FAN´s mounted per board with options for direction, voltage, location, zero slot or high velocity. Other versions available for cPCI 6U and PC104/PCI-104, and VME 6U
7/2019 New Hardware Release Dynamic Engineering has released a new SpaceWire model - PCIe-SpaceWire. PCIe-SpaceWire implements SpaceWire [ECSS-E-ST-50-12C specification] in a convenient PCIe format. Four fully independent and highly programmable SpaceWire ports are provided by the PCIe-SpaceWire design. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point with token based flow control. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. PCIe-SpaceWire provides a bridge from PCIe ⇔ SpaceWire. Port based DMA offloads the CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the HW manuals for detailed information. 200 MHz. Link rate, industrial temperature, DMA support, Windows, Linux, VxWorks support.
6/2019 New Driver Package Windows 10 for IP-Parallel-IO family now available - TTL model with 48 independent TTL lines, -485 model with 24 differential pairs, and the 5 versions with mixed differential and single ended. Each model has two built in timers, interrupts, synchronization, register based IO. Driver calls are matched with Win7 version to minimize User Application changes when transitioning to Windows 10. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
5/2019 Updated Driver and Reference SW Dynamic Engineering SpaceWire has an updated Linux Driver [1.1.1]. The driver has been validated on an i7 Ubuntu server running 3.8.0-42 kernel (64 bit) SMP P2020 (32 micro-controller) running 2.6.35 (32 bit) SMP. All 6 models of SpaceWire have been fully tested using the current FLASH release. Tested over the frequency range up to and including 200 MHz. HW/SW architecture supports full duplex line rate processing of back-to-back packet streams. PCI lane steering, driver auto detects endianess and controls HW accordingly. The updated FLASH supports improved DMA operation - changes made to improve port throughput and leveling of PCI access. Improved performance with small packets by adding to flow control. Please see the Hardware manuals for these details. Line rate testing with the new Linux and Flash combination yielded 50 MBytes/sec continuous.
5/2019 Updated Driver and Reference SW Dynamic Engineering IP Carriers and IP-Generic now have Win10 support. The carrier driver works with IP Module drivers to support any installed IP´s. IP-Generic is used with Dynamic Engineering IndustryPack carriers to faciliate use with third party IP Modules. Read, Write, Interrupts, Readfile, Writefile operations are supported along with all IP "Spaces". Support to access and control the adapter to set slot frequency, enable interrupts, check status etc. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP See new releases for IP Module Support. Manuals are available on each of the Carrier pages. Drivers support all DE carrier functions - selecting 8 or 32 MHz per position, reading IDPROM, 32 and 64 bit automatic data width conversion, byte swapping etc.
5/2019 Updated Driver and Reference SW IP-PULSE is now supported with Win10 driver and reference SW. IP-Pulse features four independent pulse generators with TTL, 422, and mixed Output options. Synchronization between generators, phase shifting during operation to simulate acceleration or deceleration, programmable number of pulses output or continuous mode, time asserted, time deasserted, and inverted options. Interrupt per pulse or completion of programmed number of pulses. The driver and reference SW package supports API programming and includes a user interface to program pulse generation. The user interface provides a simple method to use IP-Pulse as a test asset without writing any software. Features like pressing a key to repeat the programmed pulse train are handy when debugging with a scope. All of the basic features contained in the API are supported. Please see the Hardware, Software, and Quick Start guide for the details. Download from the product page.
The IP-Pulse module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
4/2019 New Adapter Use UARTcable8 to convert / adapt PMC-BiSerial-VI-UART to standard DB9 connectors. Up to 8 ports of LVDS, RX-485, RS-422 UART protocol hosted by PMC-BiSerial-VI are converted from a SCSI connector system to DB9 using industry standard pinouts. Available to direct mount or with a chassis [DIN Rails]. ROHS and Non-ROHS, conformal coating options.
4/2019 New Product PC104p-BiSerial-VI
4/2019 Updated Driver and Reference SW IP-PULSE is now supported with Win7 driver and reference SW. IP-Pulse features four independent pulse generators with TTL, 422, and mixed Output options. Synchronization between generators, phase shifting during operation to simulate acceleration or deceleration, programmable number of pulses output or continuous mode, time asserted, time deasserted, and inverted options. Interrupt per pulse or completion of programmed number of pulses. The driver and reference SW package supports API programming and includes a user interface to program pulse generation. The user interface provides a simple method to use IP-Pulse as a test asset without writing any software. Features like pressing a key to repeat the programmed pulse train are handy when debugging with a scope. All of the basic features contained in the API are supported. Please see the Hardware, Software, and Quick Start guide for the details. Download from the product page.
The IP-Pulse module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
4/2019 New Product XMC-UNIV-TEST Ever need to access to the component side of an XMC? Now you can - install XMC vertically with the component side exposed. Up to 8 lanes (PCIe) supported. Headers for JTAG, I2C, switch to set Global Addresses, and extra grounds(8). +12V and 3.3V routed with VPWR tied to 12V. Header for -12V. SCSI connector plus header to support Pn6 IO. Compatible with HDEterm68 for breakout or loop-back.
4/2019 Updated Driver Package Linux for Dynamic Engineering IndustryPack Carriers and Modules. Full suite of IndustryPack carriers and expanded module support. IP-Parallel-IO family now supported - -TTL model with 48 independent TTL lines, -485 model with 24 differential pairs, and the 5 versions with mixed differential and single ended. Each model has two built in timers, interrupts, synchronization, register based IO. Other IP models include IP-BiSerial-VI Spartan VI with 24 LVDS or 485 IO - for user specific IO requirements, IP-OptoISO-16 16 Opto coupled IO 1.5A, 60V rated, IP-Parallel-HV 24 0-30V singled ended IO. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
1/2019 Updated Driver and Reference SW IP-1553 is now supported with Win7 driver and reference SW. Control all aspects of the single or two port models. Each port is dual redundant with strapping options for direct and transformer coupled operation. The IP-1553 module driver is used with Dynamic Engineering IndustryPack carriers/drivers. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
11/2018 Updated Driver and Reference SW IP-Generic now has updated Win7 driver and reference SW support. IP-Generic is used with Dynamic Engineering IndustryPack carriers to faciliate use with third party IP Modules. Read, Write, Interrupts, Readfile, Writefile operations are supported along with all IP "Spaces" Support to access and control the adapter to set slot frequency, enable interrupts, check status etc. For use with PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP
10/2018 Updated Driver and Reference SW PMC-BiSerial-III-RL1 now has Win7 driver and reference SW support. Windows 7, 64 and 32 bit reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PMC-BiSerial-III-RL1 along with reference software showing how to use the drivers to control the interface. PMC-BiSerial-III-RL1 provides eight UART I/O channels each consisting of RS-485 transmit and receive data. The UART interface uses a 16x clock to detect received data bits. The interface can operate at up to 10 Mbits/second using a 160 MHz clock. Programmable PLL reference. DMA is supported for each channel independently. Each UART channel has 1K x 32 FIFO for transmit and another 1Kx32 for receive. Please see the hardware manual for the details.
9/2018 Updated Driver and Reference SW PMC-BiSerial-III-HW2 now has Win7 driver and reference SW support. Windows 7, 64 and 32 bit reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PMC-BiSerial-III-HW2 along with reference software showing how to use the drivers to control the interface. PMC-BiSerial-III-HW2 features 8 channels of the HW1 protocol, plus 24 blocks of Asynchronous or SDLC IO. SDLC takes 4 blocks per channel [up to 6 ports] and the Asynchronous takes two [up to 12 ports]. Each HW1 channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 blocks. The SDLC channels are programmable for frequency using the PLL. The Asynchronous channels are designed with a UART style protocol. Please see the hardware manual for the details.
9/2018 New Product PMC-UNIV-TEST Install your PMC vertically with the component side exposed for efficient use of your time. Testpoints on the PCI signals plus JTAG and extra grounds(8). SCSI connector to support Pn4 IO. ENG model has both PMC and Carrier side connectors installed to use in your system - expose PCI signals with the PMC attached to the host. Our engineers and manufacturing manager report this device is a real time saver.
8/2018 Updated Driver and Reference SW PC104p-BiSerial-III-BA14 now has Win7 driver and reference SW support. Windows 7 and Win32 reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PC104p-BiSerial-III-BA14 along with reference software showing how to use the drivers to control the interface. PC104p-BiSerial-III-BA14 features DMA operation to support a specialized serial port. 8 copies of the transmit signals. 8 inputs with software selecting which port to utilize. Status and programmable interrupts for polled or interrupt driven operation. Serial data is similar to UART but MSB first, 16/17 bits long. RS485 IO. Option for LVDS.
7/2018 Updated Engineering Kit and Hardware PCIeAlteraCycloneIV is now supplied with an updated FLASH. The Engineering Kit has been updated to compile in Quartus 17.1 [free download from Intel] and incorporate the new SFL [Serial Flash Loader] required for the new Intel FLASH device. Use our reference design as a starting point for your design. Pinouts, FLASH definition etc. are set-up and ready to use. Designed to be easy to remove our IO control and add yours. User Configurable Logic - PCIe Altera Cyclone IV 485/LVDS comes with everything you need to load your Altera program into the Cyclone IV. Fantastic for development, simulation, special purpose interfaces, multiple serial and / or parallel channels. FLASH and on-the-fly reloading for configurable and reconfigurable logic implementations.
Windows 7 and Linux reference software packages are available. Driver and Hardware Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PCIeAlteraCycloneIV along with reference software showing how to use the drivers to control the User design. PCIeAlteraCycloneIV features Cyclone IV FPGA - 115, GPIO control bus plus 16 DMA channels to support user designs based on RS-485 or LVDS IO types. A Spartan 6 FPGA handles the traffic in and out of the PCIe bus and the user has access to the Cyclone IV FPGA for their IO driven design. 40 differential pairs and 12 TTL IO are available to the user along with 24 PLL´s.
7/2018 PMC-BiSerial-VI-S311 released PMC-BiSerial-VI-S311 is an updated version of the original PMC-BiSerial-S311 design with an added 2nd port and new features. PMC-BiSerial-VI-S311 is supported with a Win7 driver and reference software. Linux and VxWorks available by special request. The updated design has 2 ports configured to interact with the S311 bus (Northrop Grumman RADAR). Each port is independent with programmable transmit rate, multiple interrupt options, programmable FIFO level, internal loop-back and more. The ports are RS485 based with LVDS as an option. The base design comes with bezel IO. Rear [Pn4] IO is an option. Please see the Dynamic Data Sheet [models tab] for links to HW and SW manuals with detailed information.
6/2018 Updated Support: IP-Parallel-IO is an IndustryPack supporting both Differential [RS-485, RS-422, LVDS] and single ended [LVTTL] IO types. The ordering options include: -TTL with 48 TTL IO, -485 with 24 differential pairs, and -1 through -5 with different combinations of TTL and differential IO. All IP-Parallel-IO models are now supported with Win7 driver and reference applications. IP-Parallel-IO can be adapted to a variety of systems with different IP carriers. PCIe5IP, PCI5IP, cPCI4IP, PC104p4IP are a few examples. See Dynamic Data Sheet for more information plus downloadable Hardware and Software manuals.
6/2017 Win7 driver for IP-QuadUART-485 released. IP-QuadUART-485 provides 4 UART ports each with 128 byte FIFO´s and RS-485 IO. RX, TX, RTS, CTS, DSR, DTR. XR16C854 UART device. Use the new driver and reference software with any Dynamic Engineering IP Carrier - PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI2IP , cPCI4IP, PC104p4IP are a few examples. The reference SW package includes example software using all of the major functions including operation with and without RTS/CTS performing local loop-back routines. Source supplied for reference SW to allow easy modification for your project.
4/2018 PCIe4LBPCI riser card with conversion to support PCI in PCIe position. DMA and interrupts supported. 32/25 ↣ 64/133 operation. Industrial Temperature range. Transparent Bridge. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
4/2018 PMC-OctalUART-232 features 8 (16550 compatible) UART ports with RS-232 signaling. RX, TX, RTS, CTS, DTR, DSR supported on each port. Front and rear IO options. Industrial Temperature range. Industry standard IO definitions and memory map allow PMC-OctalUART-232 to be used in place of PMC-OCTPRO-232. Win7, Linux, VxWorks support. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
3/2018 VPX8LXMC3U is used to mount an XMC into a VPX position. Options for conduction cooled or air cooled environments. REF CLK is supported along with local 100 MHz reference and high speed low jitter devices for Gen1-3 SSC and NSSC operation. Options for PMC, and/or XMC style rear IO connections. Controlled impedance, differentally routed rear IO. Industrial Temperature range. +12, 5, 3.3V, -12V supplied to installed XMC. Selectable VPWR [5V or 12V]. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
2/2018 VPX-GLIB Global Interface Board - VPX-GLIB is a multi-purpose hardware design supplying many system supervisor and space saving interfaces. VPX-GLIB is controlled via SPI bus [LVDS] using CLK, EN, SEL [2-0], MOSI, MISO. Currently the SEL encoding 000, and 001 are used for internal SPI controlled register access with SEL 010 used for conversion to SMB. The SPI interface with the CPU is received and decoded. SPI accesses to internal functions are re-routed to a second decoder which extracts data to be written or packages data to be read. The extracted data is stored into a local register, and then parallel loaded to the target register. Base design provides LVDS, 485, single ended electrical interfaces with conversion, direction and termination control. Local voltage plus external voltage measurements with 3x LM81´s, remote temperature measurement [TMP421] with automated HW interface, Multi-voltage inputs with programmable set-points. 10 MHz Clock reference testing and forwarding. Industrial Temperature range. Please see the Dynamic Data Sheet for links to HW manuals and detailed information.
12/2017 IP-BiSerial-VI-BA27 provides a programmable serial interface with transmit and receive full duplex. Data and clock signals, 16, 32 bit lengths plus programmable parity, Msb/Lsb first operation. 4Kx16 FIFO´s for each direction. RS485 standard, LVDS option. programmable operational frequency. Added features: Programmable Done Pulse at end of transmission. Programmable delay from last clock and programmable width of pulse. Software request activated pulse option too. 16 bit Parallel port with programmable direction per bit, and termination per bit. This is an update to the BA13 design and recommended for new projects. Win7 driver and reference software. Based on IP-BiSerial-VI - FPGA based with 24 independent differential IO each with programmable termination. Matched length, impedance controlled routing. Programmable PLL with 4 clock references [not implemented for BA27]. Industrial Temperature range. 8 and 32 MHz IP Module operation. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
11/2017 Win7 driver for IP-Crypto released. IP-Crypto provides an interface to KYK-13 with options for the different voltage standards. In addition the unused [by KYK-13 function] IO are provided as a parallel port with bit wise programming, interrupts etc. Use the new driver and reference software with any Dynamic Engineering IP Carrier - PCIe3IP, PCIe5IP, PCI3IP, PCI5IP, cPCI4IP, PC104p4IP are a few examples. The reference SW package include "Read-KYK" and local loop-back routines demonstrating the use of IP-Crypto.
10/2017 Linux For SpaceWire updated Version 1.09 supports the current line-up of K and BK 4 port SpaceWire boards including PMC-SpaceWire, PCI-SpaceWire, PC104p-SpaceWire. The driver and reference application were developed and tested on a Ubuntu server 64 bit server running 3.8.0-42 kernal (64bit) SMP as well as 2.6.35 (32 bit) SMP on a P2020 platform. ENET-SpaceWire uses this driver in our Router/Bridge application. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Available now.
9/2017 PCIe8LSwVPX3U updated PCIe8LSwVPX3U is an 8 lane PCIe adapter with switch isolation for VPX development. The switch isolates the spread spectrum clocking found in most PC´s from the VPX port. User selectable SSC and NSSC clocking on the VPX port. REF CLK supported [25 MHz SSC]. PCIe 3.0 compliant, 1-8 lanes can be used by the installed VPX. Local power conversion for the 3.3V and 5V rails with efficient switching power supplies. Secondary power connector can be installed for high power consumption VPX cards. 10A on 3.3V and 5V rails max. Power monitoring circuits on the VPX and switch power rails. Status indicators for switch. SMA connectors on the spare SSC and NSSC ports. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS. Available now.
8/2017 Added Support: IP-ReflectiveMemory is now supported by a Windows® 7 compatible driver. The driver and reference application "UserAp" are included with purchase of IP-ReflectiveMemory. Hardware features include operation with standard Ethernet cable, option for client cable configuration, rapid update to other nodes - up to 256 total, LVDS IO with DIODE protection, 256Kx16 RAM, ROHS and standard processing, Standard and Extended temperature. Additionally customization is possible within the Xilinx programmable logic.
8/2017 Added Support: PMC Parallel IO is now supported by a Windows® 7 compatible driver. The driver and reference application "UserAp" are included with purchase of PMC-Parallel-IO. Hardware features include 64 open drain TTL connections with options for front and rear IO, ROHS and standard processing, Standard and Extended temperature. Additionally customization is possible within the Altera programmable logic. Available since 1999, PMC-Parallel-IO is a great example of Dynamic Engineering´s commitment to our clients.
8/2017 PMC BiSerial VI UART updated PMC BiSerial UART has been updated to include higher speed operation with the PLL - now up to 4 Mbit operation. The Linux driver is now available too. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. Operational reference programmable on a port by port basis to be 32 MHz or user programmed PLL [up to 64 MHz]. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized plus alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid mode where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® and Linux with VxWorks in development. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
7/2017 Added Support: IP-Parallel-IO is an IndustryPack supporting both Differential [RS-485, RS-422, LVDS] and single ended [LVTTL] IO types. The ordering options include: -TTL with 48 TTL IO, -485 with 24 differential pairs, and -1 through -5 with different combinations of TTL and differential IO. IP-Parallel-TTL and IP-Parallel-4 are now supported with Win7 driver and reference applications. IP-Parallel-IO can be adapted to a variety of systems with different IP carriers. PCIe5IP, PCI5IP, cPCI4IP, PC104p4IP are a few examples. See Dynamic Data Sheet for more information plus downloadable Hardware and Software manuals.
7/2017 Added Support: IP-Parallel-Tape IP-Tape is a special version of IP-Parallel-TTL with a DTC tape machine interface. IP-Tape is now supported with a Win7 driver and reference application. IP-Parallel-Tape can be adapted to a variety of systems with different IP carriers. PCIe3IP, PCI3IP, cPCI2IP, PC104pIP are a few examples. See Dynamic Data Sheet for more information plus downloadable Hardware and Software manuals.
5/2017 New Design: PCIe4LHOTLinkx5 HOTLink is used in applications demanding high speed and high reliability including sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. PCIe4LHOTLinkx5 is a PCI Express card with 5 HOTLink receiver/transmitter pairs. Each of the HOTLink channels is supported with a separate DMA transfer engine plus local memory. All ports are full duplex with this design. The lower four ports are supported with a VHDCI connector. Fiber Optic controls are available on the connect to allow use in a Fiber System. The 5th port is supported with coax connectors. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames [indepedent each channel]. The first client version is optimzed for data reception from high speed A/D´s. Win7 driver and reference application available. See Dynamic Data Sheet for more information and manuals.
5/2017 New Design: PCIe8LXMCX2CB Adapt 1 or 2 XMC´s into a PCIe system with PCIe8LXMCX2. A 24 lane switch is used to provide 8 PCIe lanes to each of the XMC positions. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Internal XMC interconnect bus PCIe8LXMCX2CB is ported from PCIe8LXMCX2 and resistors added to allow for internal connections between the XMC Jn4/Jn6 connectors. 4 resistors at each Jn6 pin to allow connection between the XMC´s and or the SCSI/DIN connector IO. Almost zero stub length, matched length impedance controlled routing. Standard differential pair definitions. A detailed selection map is available in the manual. See Dynamic Data Sheet for more information and manuals.
5/2017 PMC BiSerial VI UART updated PMC BiSerial UART has been updated to include RTS/CTS flow control. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. Operational reference programmable on a port by port basis to be 32 MHz or user programmed PLL. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized and now an alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid mode where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® with Linux and VxWorks in development. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
5/2017 Product Update: IP-OptoISO-16
IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FET´s. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. IP-OptoISO-16 is configured to support high and low side switching. Each switch is independent for mixed mode operation. Win7, Linux, and VxWorks driver and reference application available. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Two Timer Counters which can be used for system timing or to create output waveforms. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-OptoISO-16 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
5/2017 Product Update: PCI2cPCI family
PCI2cPCI adapters allow the user to install a cPCI module into a PCI slot. A new version is available : PCI2cPCI-32-IO joins the PCI2cPCI-32 and PCI2cPCI-64 versions. The new -IO model provides headers connected to the cPCI module J2 IO signals. The headers can be accessed with standard header cables. A handy device for development and test situations. The cPCI module is installed externder card fashion - directly over the short connector adapter. All standard signals supported - DMA, Interrupts etc. Proper impedance on all signals. Extended area on PCB marked as no copper to support user modifications as needed. Please see the Dynamic Data Sheet for links to HW manual and detailed information.
4/2017 Product Update: IP-OptoISO-16
IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FET´s. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. IP-OptoISO-16 is configured to support high and low side switching. Each switch is independent for mixed mode operation. Win7 and Linux driver and reference application available. VxWorks in development. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Two Timer Counters which can be used for system timing or to create output waveforms. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-OptoISO-16 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
4/2017 PMC BiSerial VI UART updated PMC BiSerial UART has been updated with a port by port option to use the on-board PLL. More frequencies can be generated between the options for 32 MHz reference and 4 PLL inputs. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. Operation from 2 MHz down. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized and now an alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid mode where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® with Linux and VxWorks planned. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
4/2017 New Release: PCIe4LXMCX1 Available now. Adapt an XMC into a PCIe system with PCIe4LXMCX1. 4 PCIe lanes routed to the XMC. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Ported from the popular 8 PCIe lane version PCIe8LXMCX1 to allow users to implement in the shorter x4 PCIe positions when their XMC does not use 8 lanes. See Dynamic Data Sheet for more information and manuals.
4/2017 IP-Parallel-HV IP-Parallel-HV incorporates 24 open collector drivers to allow a wide range of external voltages to be controlled. A local regulator can be programmed for voltages up to 12V, and an external reference used for voltages up to 30V. Resistor networks divide the external voltages to allow 24 0-30V inputs to be accepted. Programmable interrupts on each receiver. Updated SW is now available for Windows, Linux and VxWorks. There is plenty of room in the FPGA for custom filtering etc. IP-DEBUG-BUS is a recommended accessory.
3/2017 PMC BiSerial VI UART PMC BiSerial UART has been updated and moved to the PMC BiSerial VI platform. The UART has 8 ports and operates with RS485 or LVDS IO. Each port is independently programmable for baud rate, 7/8 bits, parity[yes, no] [odd, even, level], number of stop bits etc. 32 MHz reference frequency allows operation from 2 MHz down to 150. Each port has independently programmable interrupts, and status for polled operation if that is preferred. Selectable modes per port include unpacked, packed, packetized and now an alternate packetized and test mode. Unpacked is a traditional UART with 8 bits per write/read. Packed is more efficient with 4 bytes per word written/read. Packetized is a hybrid where packed data is loaded with the last LW having any number of bytes and a separate packet descriptor controlling the transfer. Alternate Packetized mode incorporates the descriptor into the data as the 4th byte per LW. Test mode allows SW to create the character to be sent - 16 bit data with a count to allow a string of dissimilar formatting to be transmitted - mainly for system test etc. where errors on demand are needed to check error detection. All modes are supported with 255x32 FIFO´s and DMA. With DMA, transfers larger than the FIFO size can be scheduled with a single interrupt at the end. In addition inter-packet timing can be controlled as well as restart of packet transmission with programmable timers. Currently supported for Windows® with Linux and VxWorks planned. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
2/2017 PC104p Chassis web page now has two "movies" showing disassembly and assembly of the external and internal chassis. The chassis are designed to house multiple PC104, PCI-104, PC104p, PCIe104 devices. A rugged container suitable for harsh environments. Power Supplies, Fan cards, IO and other support available.
2/2017 PMC-MC-X2 and PMC-MC-X4 Chassis web page now has two "movies" showing disassembly and assembly of the chassis. The chassis are designed to house two or four PMC devices. The PMC´s are mounted on the top and bottom of the motherboard for high density packaging. The motherboard supports the basic PCI functions with power supplies, arbitration, interrupt routing, fan cooling with speed control etc.
Front and Rear View of 2 position RIO version of the PMC Mini Carrier Chassis
2/2017 IP-BiSerial-VI is Dynamic Engineering´s latest IndustryPack®. It is FPGA based with 24 independent differential IO each with programmable termination. Matched length, impedance controlled routing. Programmable PLL with 4 clock references. Industrial Temperature range. 8 and 32 MHz IP Module operation. Windows, Linux, and VxWorks drivers and reference software. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. Two models released - CTRB with software selectable Counter Timer and One-Shot modes - 8 ports per module, and SIB with two software selectable serial interfaces.
11/2016 VPX2IP is Dynamic Engineering´s latest PCIe native FPGA based IndustryPack Module adapter/carrier - this time for VPX. VPX2IP is a 3U 4HP mechanical configuration with two IP Module locations. Front Panel IO is standard utilizing two 50 position box headers with ejectors at the VPX bezel. Compatible with standard 50 pin ribbon cable and discrete wiring systems. Rear Panel IO is also available with IP module IO routed to the VPX rear connector [P2/J2]. Multi-word transfers are supported: 64, 32, 16, and 8 bit transfers are easy to implement with standard CPU´s. VPX2IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range, 8 and 32 MHz IP Module operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. PCIe single lane operation. Windows, Linux, and VxWorks drivers and reference software. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information.
11/2016 PCIe104Diff is a new PCIe native FPGA based design providing DMA or standard R/W operation. "DIFF" provides 18 differential transceivers which can be populated with LVDS or RS-485 compliant [or a mix] interface devices. The FPGA is supported with SDRAM, triple output PLL, and oscilator. The transceivers are fully suported for independent operation with programmable termination and direction for each transceiver. Stackable technology. PCIe adapter is available for use within a PC. The initial client design "OS1" uses a serial interface operating at 150 MHz. Linux, and Windows SW packages. See Dynamic Data Sheet for more information and manuals.
11/2016 PCIe1LPCIe104 is a new PCIe adapter board to allow mounting a 1 lane PCIe104 device in a standard PC. Two positions are provided to allow operation in a production orientation - PCIe legal mechanical, or in a test orientation with the PCIe104 device mounted above the extender card for ease of access. The PCIe interconnection is through a Gen 3 mux to prevent stubs to the unused position. Local power supply for the 5V rail on the PCIe104. 1/2 length PCIe card with option for zero slot fan. Gen1-3 PCIe supported. See Dynamic Data Sheet for more information and manuals.
10/2016 DESWBO now includes an International power supply. Adapters for many common non-US systems are accomodated with the included adapters. DESWBO is the Dynamic Engineering SpaceWire BreakOut and is used for monitoring and debugging SpaceWire links. DESWBO is inserted between two nodes to track FCT´s, various error conditions, traffic being passed. Test points are provided for direct monitoring of the received SpaceWire signals.
See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Combined with the IP Module driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
9/2016 cPCI2IP Win7 unified driver released for cPCI2IP. Driver comes with install files for driver plus reference software using cPCI2IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of cPCI2IP. Supports new features with Rev G1 FPGA. PROM updates are available.
See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Combined with the IP Module driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
9/2016 Product Update: IP-OptoISO-16
IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FET´s. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. IP-OptoISO-16 is configured to support high and low side switching. Each switch is independent for mixed mode operation. The new revision 04 of the PCB supports the Spartan II FPGA. The new FPGA can support additional client requested functionality. The new design is compatible with the previous revisions. Win7 driver and reference application available. Linux and VxWorks in development. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Two Timer Counters which can be used for system timing or to create output waveforms. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-OptoISO-16 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
9/2016 Updated Design: PCIe8LXMCX2 Adapt 1 or 2 XMC´s into a PCIe system with PCIe8LXMCX2. A 24 lane switch is used to provide 8 PCIe lanes to each of the XMC positions. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Now updated to allow user selection of delayed, immediate, and disabled for the +5V and +3.3V internal power supplies. If your XMC does not use one of the rails your inrush requirement can be reduced by disabling the unused supply. If your system has slow to program devices you will want the immediate turn on setting, and if your device is faster to load you can space out the inrush of the local supplies with the delayed setting. See Dynamic Data Sheet for more information and manuals.
9/2016 Updated Design: PCIe8LXMCX1 Adapt an XMC into a PCIe system with PCIe8LXMCX1. 8 PCIe lanes routed to the XMC. Options for FAN´s, rear IO connector types, and added external power. Bezel IO also supported. Internal Power Supplies for +5V, 3.3V, and -12V. +12V routed from PCIe interface. Now updated to allow user selection of delayed, immediate, and disabled for the +5V and +3.3V internal power supplies. If your XMC does not use one of the rails your inrush requirement can be reduced by disabling the unused supply. If your system has slow to program devices you will want the immediate turn on setting, and if your device is faster to load you can space out the inrush of the local supplies with the delayed setting. See Dynamic Data Sheet for more information and manuals.
9/2016 Updated Design: PCIe4LHOTLinkx6 HOTLink is used in applications demanding high speed and high reliability including sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. PCIe4LHOTLinkX6 is a PCI Express card with 6 HOTLink receiver/transmitter pairs. Each of the HOTLink channels is supported with a separate DMA transfer engine plus local memory. The lower 4 channels are 1/2 duplex and the upper 2 full duplex. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames [indepedent each channel]. Win7 driver and reference application available. Linux and VxWorks in development. See Dynamic Data Sheet for more information and manuals.
8/2016 IP-429-II Use IP-429-II to interconnect with your ARINC 429 Bus. Act as a transmitter and/or receiver with up to 4 Transmitters and 8 receivers per IP device. Standard and custom frequencies on the 429 bus. FIFO support on transmitter. Win7 driver and reference application available. Linux and VxWorks in development. See Dynamic Data Sheet for more information and manuals. 8 and 32 MHz IP Module interface, programmable interrupt/polled modes, Time Tagging of received data with 32 bit tag, 1 uS resolution. LW aligned transmit and receive ports to optimize 32 bit auto-incrementing accesses. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP-429 Module. IP-DEBUG-BUS is a recommended accessory to support initial development.
8/2016 IP-HV-TEST Use IP-HV-TEST to develop a driver or test an IP Carrier, IP-HV-TEST is based on the IP-Parallel-HV IndustryPack module with a special FLASH load. The Module responds to all 4 access types, allows testing of both interrupts, has 2K bytes of RAM and more to support your SW or HW development. IO, INT, MEM and ID spaces are supported along with interrupts etc. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module. IP-DEBUG-BUS is a recommended accessory.
7/2016 IP-Generic Win7 manual for is now posted on each of the 8 IP Carrier pages with Win7 support. IP Generic allows the client to communicate with IP Modules not supported with specific IP Drivers. IO, INT, MEM and ID spaces are supported along with interrupts etc. Combined with the carrier base driver the user can select the IP reference clock [8 or 32], endianness support, and other carrier level features plus control/program the IP Module.
7/2016 PCIe3IP Win7 unified driver released for PCIe3IP. Driver comes with install files for driver plus reference software using PCIe3IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 3 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCIe3IP.
6/2016 PC104pIP Win7 unified driver released for PC104pIP. Driver comes with install files for driver plus reference software using PC104pIP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PC104pIP.
6/2016 PCIe5IP Win7 unified driver released for PCIe5IP and first units of PCIe5IP shipped. Driver comes with install files for driver plus reference software using PCIe5IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 5 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCIe5IP.
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PC104p-Chassis HW mounting System 6/16 A handy addition to your PC104 chassis is the ability to mount SSD and other non-PC104 stack HW within your stack system. Designed to work with the inner frame to create a mounting system for Solid State Drives [SSD] and other non-PC104 stack hardware within the chassis. 1-4 shelves per Shelving Unit can be used. Captured fasteners are used to mount the shelf to the inner end plates. Please see the manual for the mounting hole pattern supplied on the shelf. Inter-shelf gap of 1 in. |
5/2016 PMC-MC-X2-RIO-BA25 Configured version of chassis / motherboard using 2020 based CPU and HDLC interface to create an ethernet / HDLC bridge for remote HDLC configuration, control and data transfer. See under Customized tab on Dynamic Data Sheet for PMC-MC-X2 Chassis. Linux applications developed with Ubuntu. Targeted application is HDLC ⇆ Ethernet [local or long haul]⇆HDLC with the BA25 taking care of the HDLC⇆Ethernet conversion on each end. A packet Server application was developed to manage the traffic between the BA25´s.
5/2016 PC104p4IP Win7 unified driver released for PC104p4IP. Driver comes with install files for driver plus reference software using PC104p4IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 4 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PC104p4IP.
5/2016 cPCI4IP Win7 unified driver released for cPCI4IP. Driver comes with install files for driver plus reference software using cPCI4IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 4 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of cPCI4IP.
5/2016 cPCI2IP Win7 unified driver released for cPCI2IP. Driver comes with install files for driver plus reference software using cPCI2IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for both positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of cPCI2IP.
5/2016 PCI3IP Win7 unified driver released for PCI3IP. Driver comes with install files for driver plus reference software using PCI3IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 3 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCI3IP.
5/2016 PCI5IP Win7 unified driver released for PCI5IP. Driver comes with install files for driver plus reference software using PCI5IP with IP-TEST. Full ATP operation with ID, IO, Memory, Interrupt spaces tested for all 5 positions. In addition IP-Generic is included allowing use of the driver with 3rd party IP modules. Included with your order of PCI5IP. PCI5IP has recently been qualified in the Magma external chassis. Overnight testing with multiple PCI5IP´s each with IP-Test installed. More than 3 million memory tests performed per card without issue. [Billions of operations over the course of the walking ones etc.]
3/2016 PMC-MC-X2 Manual released for Rear IO version. - PMC-MC-X2 has a new version featuring rear IO. VHDCI connectors are used along with matched length, impedance controlled, differential routing from Pn4 of each PMC position to the rear of the motherboard. In addition the power supplies have been updated to handle 10-40V input power. Temperature based Fan control for 12V fans. The standard features for arbitration, PCI clock generation, interrupt handling etc. are retained. An updated version of the chassis is also available with the rear IO and rear status LED´s. PMC-MC-X2 has two PMC positions where the intallation is back-to-back sandwiching the motherboard. The overall package is not much larger than the two PMC´s. Install a PrPMC in position 0 and your IO device in Position 1 for a compact, rugged, industrial temp [depending on PMC´s] solution.
2/2016 PCIe8LXMCX2 has been updated. New features include (1) option of having either, neither or both rear IO connectors [J6, J4] installed (2) user shunt selection to enable or disable the 3.3V and 5V power supplies independently, and to select a delayed or immediate start-up for those power supplies. A delayed start-up can help reduce in-rush requirements in your system while immediate start-up may be desired for fast embedded systems. PCIe8LXMCX2 is an 8 lane PCIe compatible board with 2 XMC positions. The PCIe "gold finger" connections are routed to the switch and to the XMC´s with impedance controlled differential traces. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4/Pn6 to either DIN or SCSI connector. Available now.
2/2016 Windows® Driver for BA16 An updated driver for the BA16 version of the PMC-Parallel-TTL and XMC-Parallel-TTL designs has been released. The updated driver is optimized for WDF [Windows 7 and later] projects and includes the driver, installation files, and reference application. BA16 has the standard features of PMC-Parallel-TTL plus: two synchronous parallel ports - 8 bits with reference clock and strobe. DMA support with 4Kx32 FIFO on RX, and 2Kx32 FIFO on TX. Driver has utilities for programming the PLL using the "JED" file. The driver is included with purchase of PMC-Parallel-TTL-BA16 or XMC-Parallel-TTL-BA16.
2/2016 SpaceWire Cables Two new versions have been released bringing the total variations of our SpaceWire cables to 11 types. The basic SpaceWire cable is male to male with TX-RX cross-over incorporated. Variations include male-to-female with 1:1 wiring to support bulkhead implementations, various plating options, male-to-female with cross-over etc. All can be ordered to custom length requirements.
2/2016 PCI-ALTERA Win7 driver - PCI-Altera is a user programmable design featuring 40 differential IO [can be 485 or LVDS] 12 TTL IO, 8 PLL´s 8 TX and 8 RX channels with DMA support. PCI-Altera has a 20K400E Altera device for the user design. [ PCIeAlteraCycloneIV is recommended for new designs.] Many clients have PCI-Altera installed into systems requiring OS updates. New Windows® 7 compliant driver and user application packages are available to support these legacy systems. A limited number of PCI-Altera boards are available for purchase. PCIeAlteraCycloneIV is production status.
2/2016 PMC-MC-X2 Updated Version - PMC-MC-X2 has a new version featuring rear IO. VHDCI connectors are used along with matched length, impedance controlled, differential routing from Pn4 of each PMC position to the rear of the motherboard. In addition the power supplies have been updated to handle 10-40V input power. Temperature based Fan control for 12V fans. The standard features for arbitration, PCI clock generation, interrupt handling etc. are retained. An updated version of the chassis is also available with the rear IO and rear status LED´s. PMC-MC-X2 has two PMC positions where the intallation is back-to-back sandwiching the motherboard. The overall package is not much larger than the two PMC´s. Install a PrPMC in position 0 and your IO device in Position 1 for a compact, rugged, industrial temp [depending on PMC´s] solution.
12/2015 HDEterm68 Updated Version - HDEterm68 now has internal planes to provide impedance controlled routing for better perfomance. Matched length, differentially routed, impedance controlled traces from SCSI to breakout to SCSI. Options for horizontal and vertical connectors plus mixed as well as with a DIN rail enclosure or for stand-off mounting. The ENG version has strategically placed footprints to allow for termination, isolation, signal injection, plus footprints for an oscillator, differential transceiver [RS485, LVDS], and more. A popular board with uses in loop-back testing, break-out for plant / system operation, system simulation etc.
12/2015 PCI-NECL-II-STE3A Re-Engineered - "STE3A" 8 bit parallel data path - full duplex - [NECL input and output] with reference clock and enable. Data valid on falling edge of clock, enable active high. Programmable boundary SDRAM configured as FIFO (32 Mbytes), DMA support, 12 bits GPIO (TTL). Updated with higher performance memory operation, increased FIFO size, added status, and operational enhancements. Linux Drivers plus reference applications available - including multi-board support. Manuals are available on the Dynamic Data Sheet. Cross over and straight connection D100 cables are available.
10/2015 PMC BiSerial III New version - "SDLC" SDLC provides 8 full duplex channels of Synchronous Data Link Control interface. Each channel has separate 4K Byte Rx and Tx Dual Port RAM based circular buffers. Linux and Windows Drivers plus reference applications available. Manuals are available on the Dynamic Data Sheet.
9/2015 PCIeBiSerialDb37 New version - "L3COM1" L3COM1 provides a byte wide half duplex port with flow control. LVDS IO is standard. More than 1 MByte of storage for the receive direction. DMA. PLL programmable for a range of frequencies. Packetized and FIFO level based operation. Packets allow for byte length programming while retaining the advantages of LW packed data. Programmable padding between received packets. Tested at 40 MHz. Hardware and Linux support manuals are available on the Dynamic Data Sheet.
8/2015 PCIe3IP Updated PCIe3IP is ready to order. Now even faster. Multi-word transfers are now supported, incorporating the 32 bit to 16 bit conversion familiar from the PCI3IP, PCIe3IP also handles longer transfers up to 64 words. 64, 32, 16, and 8 bit transfers are easy to implement with standard CPU´s. PCIe3IP is a 3 position adapter for IndustryPack devices. PCIe3IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range, 1/2 length, 8 and 32 MHz operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. PCIe single lane operation. Compatible with standard 50 pin ribbon cable and discrete wiring systems. Linux and Windows drivers and reference software available. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS.
6/2015 PMC XM DIFF has been updated. PMC XM DIFF is designed for client designed applications. PMC XM DIFF has a built in PCI interface with DMA to support the client design within a Virtex LX60. The recently updated design has improvements for manufactability, through-put, programming options and additional status. Supported with Windows®7 drivers, reference application SW and starter design [VHDL]. 34 differential pairs with RS485, LVDS or a mixture. Option for Bezel or Rear IO. Matched length, impedanced controlled IO routing. Includes temperature sensor, and user Dip Switch. Available now. Linux and VxWorks coming
6/2015 PCIe8LXMCX1 PCIe8LXMCX1 has been updated. New features include (1) option of having either, neither or both rear IO connectors [J6, J4] installed (2) user shunt selection to enable or disable the 3.3V and 5V power supplies independently, and to select a delayed or immediate start-up for those power supplies. A delayed start-up can help reduce in-rush requirements in your system while immediate start-up may be desired for fast embedded systems. PCIe8LXMCX1 is an 8 lane PCIe compatible board with 1 XMC position. The PCIe "gold finger" connections are routed to the XMC with impedance controlled differential traces. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4/Pn6 to either DIN or SCSI connector. Available now.
4/2015 PCIe8LSwVPX3U The switched version of PCIe2VPX3UX4 is now available. PCIe8LSwVPX3U is an 8 lane PCIe adapter with switch isolation for VPX development. The switch isolates the spread spectrum clocking found in most PC´s from the VPX port. PCIe 3.0 compliant, 1-8 lanes can be used by the installed VPX. Local power conversion for the 3.3V and 5V rails with efficient switching power supplies. Secondary power connector can be installed for high power consumption VPX cards. 10A on 3.3V and 5V rails max. Power monitoring circuits on the VPX and switch power rails. Status indicators for switch. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS. Available now.
3/2015 PCIe3IP The PCIe version of PCI3IP is now available. PCIe3IP is a 3 position adapter for IndustryPack devices. PCIe3IP has built in power supplies with fused filtered power to the IP positions, independent IP buses, Industrial Temperature range, 1/2 length, 8 and 32 MHz operation. The independent IP module buses allow for parallel processing of IP accesses for higher performance. 32 bit accesses are automatically processed with dual IP operations. PCIe single lane operation. Compatible with standard 50 pin ribbon cable and discrete wiring systems. Linux and Windows drivers and reference software available. Please see the Dynamic Data Sheet for links to HW and SW manuals and detailed information. On-line storefront is also available from the DDS.
3/2015 SpaceWire "BK" The PCI version of SpaceWire has a new update available BK. Version BK make use of the greater resources in the Spartan 6 FPGA to increase FIFO size, increase top speed, provide Industrial Temperature operation, and add new features. Add "-BK" to the PN to receive the BK version. Revision K will continue to be available for clients with on-going projects. The SpaceWire drivers are updated to provide Windows, Linux, VxWorks support for model BK. The PMC, ccPMC, PCI-104 models will be enhanced to offer BK functionality. For more details please download the hardware manual for the BK version. Available on the SpaceWire summary page.
3/2015 New HW Release VPX-6U-COOL joins VME-6U-COOL to provide cooling to VPX and VME 6U hardware. Up to 12 FAN´s mounted per board with options for direction, voltage, location, zero slot or high velocity. Other versions available for cPCI and PC104/PCI-104.
1/2015 New Driver Release PCIeAlteraCycloneIV Windows 7 compliant 32 and 64 bit drivers along with UserAp reference software have been released. Windows and Linux Driver Manuals are available for download. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. Both drivers are available to clients of PCIeAlteraCycloneIV along with reference software showing how to use the drivers to control the User design. PCIeAlteraCycloneIV features 16 DMA channels to support user designs based on RS-485 or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the PCIe bus and the user has access to the Cyclone IV FPGA for their IO driven design. 40 differential pairs and 12 TTL IO are available to the user along with multiple PLL´s.
12/2014 Updated Manual Release PCIe4LHOTLinkx6 Revision A of the Windows Driver and Revision 2.0.0 of the Linux Driver Manuals have been released. Both drivers are available to clients of PCIe4LHOTLinkx6 along with reference software showing how to use the drivers to control the HOTLink design. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. PCIe4lHOTLinkx6 features up to 6 HOTLink connections with PECL or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the HOTLink transmitters/receivers. The base version has programmable sync patterns [up to 3 characters in series to cause sync to be achieved], deep FIFO´s, independent DMA operation for each channel, PLL support and more. One RJ45 connector has 4 half duplex connections, and the other 2 full duplex connections.
12/2014 Updated Driver Release SpaceWire Windows 7 driver for revisions up to K. The driver and reference software are used with Dynamic Enginerering SpaceWire interface hardware including ccPMC-SpaceWire, PMC-SpaceWire, PCI-SpaceWire, PCI-104-SpaceWire. Linux and VxWorks drivers and reference software are also available for revision K SpaceWire hardware.
12/2014 Updated Manual Release PCIe4LHOTLinkx6 Revision C of the Hardware manual has been released. Please refer to the HW manual for memory maps, bit maps, operational descriptions, capabilites, pinouts etc. Click on the MANUALs button under the product photo on any Dynamic Data Sheet to jump to that products´ manuals. PCIe4lHOTLinkx6 features up to 6 HOTLink connections with PECL or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the HOTLink transmitters/receivers. The base version has programmable sync patterns [up to 3 characters in series to cause sync to be achieved], deep FIFO´s, independent DMA operation for each channel, PLL support and more. One RJ45 connector has 4 half duplex connections, and the other 2 full duplex connections. Windows and Linux drivers and reference software available.
10/2014 Updated Product Release PCI2PMC Industry standard passive PMC adapter for PCI bus installations has been updated to revision K. Now Shipping. New additions to the feature list include user selectable grounding options for the PMC and PCI bezels [separately], enhanced header placement, and miscellaneous manufacturing updates. Please refer to the manual [PDF] for more information.
9/2014 New Product Release PCIe4LHOTLinkx6 features up to 6 HOTLink connections with PECL or LVDS IO types supported. A Spartan 6 FPGA handles the traffic in and out of the HOTLink transmitters/receivers. The base version has programmable sync patterns [up to 3 characters in series to cause sync to be achieved], deep FIFO´s, independent DMA operation for each channel, PLL support and more. One RJ45 connector has 4 half duplex connections, and the other 2 full duplex connections. Windows and Linux drivers and reference software available.
9/2014 Updated Product Release PCIBPMCX1 has been updated for improved fan placement, improved performance, and improved manufacturability. PCIBPMCX1 uses a PCI/PCI-X bridge to interconnect the installed PMC and the computer bus. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The Pn4 connector is routed to a SCSI connector with matched length differential routing and 100 ohm impedance.
9/2014 Updated Product Release PCIBPMCX2 has been updated for improved fan placement, improved performance, and improved manufacturability. PCIBPMCX2 uses a PCI/PCI-X bridge to interconnect the installed PMC´s and the computer bus. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The Pn4 connectors are routed to either an installed SCSI or DIN connector with matched length differential routing and 100 ohm impedance.
9/2014 New Product Release SCSI-to-SpaceWire is a cable adapter designed to connect between the "X1" line of PMC carriers and SpaceWire hardware. The cable allows SpaceWire nodes with internal to the chassis connections to be used internal to the chassis or brought out to a bezel, bulkhead or other intermediate device. User defined lengths, finishes, and SpaceWire node selection.
6/2014 Updated Product Release PC104p2PMC is an adapter to allow the use of a PMC board in a PCI-104 or PC104/p system. Dynamic Engineering has updated the design to include a path for the PMC rear IO [Pn4]. Matched length, impedance controlled differential traces connect Pn4 with P1 [SCSI]. An updated hardware manual is available on the Dynamic Data Sheet including an interconnection table. PC104p2PMC allows users to add a PMC to their PCI-104 stack. Bezel and rear IO supported. PC104p2PMC is a passive design. 4 stack postions are supported with switch control.
6/2014 Updated Product Release PMC-BiSerial-III-HW2 Dynamic Engineering has updated the HW2 version of PMC BiSerial III to improve SDLC performance. Changes include updating the Dual Port RAM memory manager to allow for continuous operation. HW2 has SW programmable operation with support for SDLC, Async [UART], and HW1 protocols. Conformal coating and ROHS processing options. Win32 and Linux support. Win7 driver coming. Ask for VxWorks.
3/2014 Updated Product Release PCIBPMCX2 Dynamic Engineering has updated PCIBPMCX2 for better manufacturability and long term support. PCIBPMCX2 is an adapter / carrier for PMC´s with 2 positions on a full size PCI card. The PCI-X capable and PCI compatible bridge allows for local PCI traffic behind the bridge as well as Host interaction with the mounted PMC devices. Perfect for real time processing with a local PrPMC and IO device. PCI slots are getting harder to find, add two PMC's in one PCI slot with PCIBPMC. This update demonstrates Dynamic Engineering´s long term commitment to our clients.
2/2014 Updated Product Release ccPMC-HOTLink Dynamic Engineering has updated ccPMC-HOTLink to use a Spartan 6 FPGA providing a large boost in available gates, internal memory, and IO rates. The design is extended temperature. The first clientized version is the AP1 which focused on image capture applications. 64Kx32 receive and transmit internal FIFO´s supported with scatter-gather capable DMA. Conformal coating and ROHS processing options. Win7 driver available with options for Linux and VxWorks.
2/2014 New Product Release cPCIRepeat32 Dynamic Engineering has released cPCIRepeat32 - an extended temperature PMC carrier with PCI bus expansion. cPCIRepeat32 has a 32 bit connection to the PCI bus on cPCI J1. J2 is used to provide the secondary side of the local bridge to the backplane along with Clocks, Bus Arbitration etc. Available with or without J2 installed. Standard and ROHS options.
1/2014 New Product Release BA23 Dynamic Engineering has released the BA23 version of PMC BiSerial III. This implementation is a variant of the BAE9 design with channels 6 and 7 updated to provide a 32 bit 5 MHz UART function. Channels 6&7 have FIFO support with DMA. Programmable for frequency, parity, stop bits. Interrupt or polled opertation. Channels 0-5 have the "BAE9" capabilities. RAM based with multiple triggering options. Linux driver support.
12/2013 New Product Release BA22 Dynamic Engineering has released the BA22 version of PCIeBiSerialDb37. The design is for image data transmission. LVDS, 73.636 MHz, 2 bit serial with reference clock and sync. The transmit side has ~262Kx32 of FIFO storage, programmable line length, idle length, number of lines per frame, minimum data to start transmission, and transmission rate. An receiver is also supplied with 5Kx32 FIFO storage, Sync detection, Frame Marking, and other features. DMA on both the Rx and Tx channels.
11/2013 New Driver Release Linux driver is now available for use with PCIeAlteraCycloneIV. Validated on an i7 Ubuntu SMP server running version 3.8.0-33 x86_64 kernel (64 bit). Driver and Reference application support all operational modes. PCIeAlteraCycloneIV features a user configuratble/programmable Cyclone IV 115 device supported with 8, 3 port PLL devices, 40 differential IO, 12 TTL IO, FLASH, and 8 high speed bidirectional data links between the PCIe interface and user design. DMA is supported on all 16 channels independently. Load the Altera from FLASH [built in] or via real-time file loading. Free to Dynamic Engineering PCIeAlteraCycloneIV clients. Contact sales@dyneng.com.
10/2013 Product Release PcieAlteraCycloneIV has been released to manufacturing status. PCIeAlteraCycloneIV features a user configuratble/programmable Cyclone IV 115 device supported with 8, 3 port PLL devices, 40 differential IO, 12 TTL IO, FLASH, and 8 high speed bidirectional data links between the PCIe interface and user design. DMA is supported on all 16 channels independently. Load the Altera from FLASH [built in] or via real-time file loading. Reference VHDL, software, and drivers are available along with cables and breakouts for the "D100" connector. PCIeAlteraCycloneIV has similar base features to the PCI-Altera design and should be considered for an upgrade. Differential IO can be outfit with RS485 or LVDS or a mix of the two. Driver and reference software are available for Win32 with VxWorks, Win7 and Linux in development. PCIeAlteraCycloneIV is available now.
10/2013 Updated Manual Release SpaceWire Hardware Manual has been updated with the latest design implementation information.
9/2013 Updated Product Releases cPCIBPMC3U64ET and cPCIBPMC6UET have been updated to incorporate LC filtering on the 5V and 3.3V power rails. Some cPCI systems suffer from noisy power distribution leading to unstable operation with the add-in cards. cPCIBPMC3U64ET and cPCIBPMC6UET now incorporate LC filters on the two main power rails. The carriers allow PMC devices to be installed into cPCI systems. Both designs are industrial "ET" temperature rated. Zero Slot Fans are available.
8/2013 New Hire Dynamic Engineering welcomes Brian Davis to the engineering department. Brian is a Sr. Engineer with years of experience in the embedded market. Brian will help to expand our PCIe based design capabilities and product line.
8/2013 Updated Product Release VxWorks driver has been updated to the current VxWorks and SpaceWire revisions. Feature expansion, misc. clean-up and enhanced interrupt processing are the benefits of the new release. Free to Dynamic Engineering SpaceWire clients. Contact sales@dyneng.com.
7/2013 Updated Product Release Win7 Driver has been updated. Feature expansion, misc. clean-up and enhanced interrupt processing are the benefits of the new release. Free to Dynamic Engineering SpaceWire clients. Contact sales@dyneng.com.
7/2013 Updated Product Release HDEterm100 has been updated for better performance. Power and Ground planes have been added and the signal routing updated to be differential with impedance control, length matching. User selectable shield to ground plane connections with AC, DC, and open for each connector. In addition more options are available for voltage division and other termination schemes.
7/2013 Updated Product Release cPCIBPMC3U64ET has been updated for better performance. Power filtering on 5V and 3.3V for noisy cPCI environments. Updated 0402 capacitors for better decoupling of bridge power supplies. Now with optional "Zero Slot" fans.
7/2013 Updated Product Release cPCIBPMC6UET has been updated for better performance. Power filtering on 5V and 3.3V for noisy cPCI environments. Updated 0402 capacitors for better decoupling of bridge power supplies. Now with optional "Zero Slot" fans.
6/2013 Updated Product Release cPCI2PMC has been updated for better manufacturability. Moving to 0402 isolators allowed for shortened trace lengths. Increased current available to the PMC position. Versions with PCI32, PCI64, rear IO, Slot Zero still available. Now with optional "Zero Slot" fans.
6/2013 New Product Release PMC-BiSerial-III-HW2 has a new Linux driver available. IOCTL based Win32 drivers are also available. The HW2 version implements 8 channels of the HW1 protocol, plus 24 blocks of Asynchronous or SDLC IO. The SDLC takes 4 blocks per channel and the Asynchronous takes two. Each HW1 channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 blocks. The SDLC channels are programmable for frequency using the PLL. The Asynchronous channels are designed with a UART style protocol.
3/2013 Updated Product Release PMC-BiSerial-III has a new clientized version "BAE9" 8 10.4 Mhz UART channels with multiple trigger and retransmit capabilities. High performance driver for Linux plus IOCTL based Win32 and Win7 drivers are available.
3/2013 New Product Enhancement: Customerized version The PMC-Parallel-TTL design has been updated with a user specific version. The
BA21has 4 I2C ports with DMA support. Standard and Fast I2C operation. Write, Read, Snoop functions. Programmable Target address. 32 bit parallel port. Win32 IOCTL type driver.
1/2013 Product Development PMC XM DIFF is currently in development for a VxWorks driver. PMC XM DIFF has 34 differential IO and can be configured with RS485 or LVDS IO. User designs are loaded into a Virtex 4 FPGA - SX35 or LX60. Windows support is currently available.
1/2013 Product Release XMC Parallel TTL VxWorks Dynamic Engineering now has VxWorks support for the XMC Parallel TTL. The version supported at this time is BA16. Initial CPU target was our new FreeScale 2020. XMC Parallel TTL has 64 bidirectional IO lines. The BA16 version is configured to support two, 8 bit parallel ports with reference clock and alignment strobe.
10/2012 Shipped SpaceWire Revision I FLASH has been released. Power Management Capability has been incorporated into the configuration space. For systems using virtualization this feature is important. Other miscellaneous updates to handle situations where multiple EEP codes are received. Dynamic Engineering has SpaceWire for PMC, PCI, PC104p and with adapters supports PCIe, VME, cPCI, VPX and other board formats. Win7, Win32, Linux drivers are available.
10/2012 New Capability Dynamic Engineering has added VxWorks to our capabilities. We have purchased the "All Types" license to allow us to develop BSP´s for our products and target any supported CPU. It takes more than a license. Dynamic Engineering has VxWorks experienced Software Engineering talent on staff. Please contact us to develop a BSP for you. Our first project is a custom BSP for a "Modbus" version of the PMC-BiSerial-III.
9/2012 Shipped XMC-Parallel-TTL is now a production status board. Available now. XMC-Parallel-TTL is an XMC version of the PMC-Parallel-TTL. Common IO connector definitions make it easy to support multiple projects with similar software and cables for both PMC and XMC. Front and rear IO options, PLL, COS interrupts, flexible VPWR [+12 or +5 is fine]. The FPGA can be updated for client specific versions. 1-4 lane PCIe operation.
8/2012 Shipped PCIe8LXMCX1 is now a production status board with it´s first deliveries. Available now. PCIe8LXMCX1 is an 8 lane PCIe compatible board with 1 XMC positions. The PCIe "gold finger" connections are routed to the XMC with inpedance controlled differential traces. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4 to either DIN or SCSI connector.
7/2012 Shipped PCIe8LXMCX2 is now a production status board with it´s first delivery of 24 units. Available now. PCIe8LXMCX2 is an 8 lane PCIe compatible board with 2 XMC positions. A 24 lane switch is used to route the PCIe interface to the XMC positions. Selectable VPWR (12 or 5), +12, 3.3 supplied to XMC´s. Matched length, impedance controlled, differentially routed IO from Pn4 to either DIN or SCSI connector.
7/2012 Updated Product Release PCIBPMC is now an "ET" rated board standard. Components rated for -40 to +85C operation. Options for DIN or SCSI rear IO, Conformal coating and "Zero Slot Fans". Available now.
6/2012 Updated Product Release PMC-BiSerial-III has a new clientized version "BAE9" 8 10.4 Mhz UART channels with multiple trigger and retransmit capabilities. Win32 and Win7 drivers available. Available now.
6/2012 Updated Product Release IP-429-II is available in 4 configurations with 1,2,3 or 4 transmitters coupled with 2,4,6 or 8 receivers. Time Tag is now standard. Industrial Temperature Standard. Arinc 429 protocol. IndustryPack format card. 8 / 32 MHz IP bus operation. New lower price with more features than the original design. Available now.
6/2012 New Product Release PCIe2VPX3UX4 is ready to help you with your VPX development. Take advantage of your PC resources by hosting your VPX in a standard PCIe slot. PCIe2VPX3UX4 routes 4 PCIe lanes to the P1 VPX connector plus power to P0 and the user IO on P2 to a SCSI connector on the PCIe2VPX3UX4. 5V and 3.3V are produced with on-board power supplies for the VPX. +12V is routed from the PCIe interface. JTAG and Global Adressing support included. PCIe and P2 differentially routed with 100 ohm controlled impedance and matched lengths. Available now.
6/2012 New Product Release VPX-RCB is a "kitchen sink" design with everything you need to control digital receivers, measure voltages, take temperatures, receive high voltage signals and more. Please go to the Dynamic Data Sheet for a more complete description, photo, block diagram, and HW manual. Available now.
4/2012 Driver Update SpaceWire has an updated driver and reference software set : Linux kernal version 3.0.0-17 developed on Ubuntu distribution 11.10. Available free of charge to our SpaceWire clients. Works with PMC, PC104p and PCI SpaceWire versions.
4/2012 Driver Update ccPMC-HOTlink has an updated driver and reference software set : Linux kernal version 3.0.0-17 developed on Ubuntu distribution 11.10. Available free of charge to our PMC-HOTlink clients.
3/2012 New hires Dynamic Engineering has hired Thai Nguyen to work in the engineering group. Thai has more than 15 years of Embedded Design experience post MS. Thai is working on our update to the PCI-Altera known as PCIeAlteraCycloneIV.
1/2012 New Product Release Take the worry out of fielding your hardware. A reversed reference supply can cause a lot of damage in unprotected systems. PC104p-RPP provides Reverse Power Protection for power supplies in PC104, PCI-104, PC104p and stand-alone applications. PC104p-RPP uses FET technology to provide the protection while significantly reducing the voltage drop. "RPP" has an optional fan to aide in system cooling. Available now.
12/2011 New Product Release Windows 7® driver. Dynamic Engineering has written a Windows 7 compliant driver for the PCIe-BiSerial-DB37-RTN8 design. The driver supports standard target accesses as well as DMA. The driver is provided with a reference application to speed integration. The driver is free to clients who have purchased RTN8.
10/2011 New Product Release SpaceWire INtime Driver. Dynamic Engineering has written a driver for the TenAsys INtime real-time operating system. The driver comes with a set of reference software to speed your integration. Please see the SpaceWire Dynamic Data Sheets for more information.
10/2011 New Product Release PMC-BiSerial-3T20 is ready for your application. Based on the proven PMC-BiSerial-III, the "3T20" has 20 transformer coupled and 2 direct coupled RS-485 IO with several termination options, large SDRAM based FIFO capability, and a Spartan III FPGA with plenty of room for your application. The first clientized version "HW1" has shipped - 20 manchester encoded / decoded data streams with a dual port RAM interface.
7/2011 New Product Release PCIeBPMCX2 is ready for your application. Based on the proven PCIeBPMCX1 and ported from the PCIBPMCX2 [PCI version]; the 2 PMC slot carrier can handle your embedded computing requirements. Use a local prPMC and specialized IO together in the same slot while retaining higher level control for an expandable system architecture with real time capabilities. Alternatively, pack two PMC IO cards into one PCIe slot to save system resources.
PCIe with 4 lanes, power supplies with 9.5A on the 5V and 3.3V rails, 2 PMC positions, Zero Slot fan options, options for Ethernet and Serial ports for prPMC position, programable interrupt routing, bezel and internal IO. Please refer to the Dynamic Data Sheet for more information. Extensive load testing has been performed to verify the design and characterize operation.
6/2011 Product Release PC104p-COOL New design to add cooling fans using "Zero Slot"™ technology to your PC104, PC104p or PCI-104 stack. 5V or 12V fan operation. Reversible. First deliveries July 2011.
6/2011 Product Release PCI-ECL-II New revision to the PCI-ECL design. Recommended for new designs. Spartan 6 FPGA with PCI interface, DMA and IO state-machines. 64 Mbytes of SDRAM on board. 20 ECL out and 20 ECL in. 12 TTL IO. Phase Locked Loop with 4 programmable clocks. SDRAM can be configured as a large FIFO with programmable boundaries. Initial client design for byte wide parallel interface with bursted clock and Windows® driver delivered. Please see the Dynamic Data Sheet for more information.
5/2011 Product Release 64 bit Linux driver released for SpaceWire. Compatible with PMC, PCI, PC104p versions of the SpaceWire design.
5/2011 Product Release PCIeBiSerialDb37-RTN8 Clientized version with 1mbyte+ receive buffer for 40 MHz byte wide data stream. 48K TX buffer with programmable TX rate. DMA support both functions. 8 bit data plus clock. LVDS IO. Please see the Dynamic Data Sheet and downloadable manual for more information. Windows® and Linux support.
4/2011 Product Release PMC-MC-X4 has been updated to add client requested features. The new additions include voltage monitor circuits which test the power supply voltages for high and low limits, thermal protection - the main power supply is shut down if the board level temperature reaches a programmable limit, a separate power supply for the fans to increase the power available to the PMC´s and to continue fan operation if the thermal limit is reached, optional vertical power entry, and a fused off board power connector to allow the local supplies to be used to support external devices. Now shipping.
3/2011 News Release Paul Kirpes has been promoted to Manufacturing Manager. Paul has his BS EE from Chico State University. Paul will bring his engineering expertise to our manufacturing group ensuring engineering level solutions for our manufacturing processes.
8/2010 Product Release Pc104pPWR28 & Pc104pPWR12 have been updated to be implemented on a common PCB "PC104pPWR" The updated design features PowerPak FET´s, larger inductors, higher current ratings and lower noise.
7/2010 Product Release IP-ConnectorSaver is a new design: used to allow for taller IP Modules, and to save wear on the built in connectors when high repetitions are used - for example in test. A small PCB is used to interconnect stacked IP Module connectors. The PCB is made as small as practical and does not impinge on the IP parts surface area.
6/2010 Product Update PC104p-BiSerial-III has been updated. Updated features include an additional FLASH device to allow for larger Xilinx FPGA through Spartan 3 4000, 2 additional PLL clock inputs, improved analog isolation, new switches for Differential IO with larger bandwidth and smaller impedance.
4/2010 Product Update PCIeBPMCX1 has been updated. The power supplies have been updated to handle more current under a wider temperature range. Revision 3+ boards can handle up to 9.5A on the 5V and 3.3V rails steady state in a lab environment without additional cooling. Please refer to the Dynamic Data Sheet for more information. The FET´s and planes have been updated to take advantage of new package options with better thermal characteristics with fantastic results. Extensive load testing has been performed to verify the design and characterize operation.
4/2010 Product Update IP-ReflectiveMemory has been updated to include new features. The updated revision B4 has added control bits to provide more user control over network restart. The standard automatic master node copy to the other nodes is the default with options to suppress the automatic update. An additional option to move all RAM writes to the network allows an alternate node to refresh the system with the data in the local RAM or for multiple nodes to each handle part of the refresh action under software control.
When an active network is disconnected to add another node or one of the equipment nodes has an issue of some sort, the network will automatically detect the down situation and the subsequent re-connection. When the network is restored the Master node can automatically refresh all nodes to make sure all match or the new features can be used to allow for software management of the restart. This is a FLASH only update and can be applied to all previously purchased cards [if desired].
1/2010 New Product Announcement PCIBPC104pET is an industrial temperature range PC104p carrier for PCI bus systems. Up to 4 active PC104p cards can be installed into the stack. Both front and rear can be used to allow options for stack growth within the chassis. The design is robust with extended temperature components, impedance controlled, PCI compliant routing, heavy power planes with decoupling for the PC104p voltages. and more. With the PCIBPC104pET ( PCI Bridge PC104p Extended Temperature) adapter / carrier converter card all you have to do is install your PC104p´s onto the adapter, and plug into the PCI slot. PCIBPC104pET is a universal voltage shorter than 1/2 length PCI card. The PC104p stack can be programed to use 3.3 or 5V for VIO. The bridge provides plug and play operation.
1/2010 Product Update Announcement PMC-BiSerial-III has a another "clientized" version available the "NASA1". The design features 4 channels used for telemetry. Each channel has a different function: LADEE-LLST, NMS, UART, Manchester (Uplink and Downlink). The transmit rate is selected with a PLL allowing for custom user frequencies. Interrupts, status and error checking. LVDS is used for LADEE and RS-485 for the other IO including a 14 bit parallel port.
Dynamic Engineering News 2009 - 2000
11/2009 New Product Announcement PCIBPMCET is an industrial temperature range PMC carrier for PCI bus systems. The design is robust with extended temperature components, impedance controlled, PCI compliant routing, matched length differentially routed IO, zero bus stub options for high speed Ethernet and Serial ports, heavy power planes with decoupling for the PMC voltages. and more. For high power applications the "Zero Slot Fans"™ are available. With the PCIBPMCET ( PCI Bridge PMC Extended Temperature) adapter / carrier converter card all you have to do is install your PMC onto the adapter, and plug into the PCI slot. PCIBPMCET is compatible with both 64 and 32 bit PCI slots. PCIBPMCET is a universal voltage 1/2 length PCI card. The PMC slot can be programed to use 3.3 or 5V for VIO. The bridge provides plug and play operation.
11/2009 Product Update Announcement PMC-BiSerial-III has a another
10/2009 Product Update Announcement IP-Parallel-IO Windows® driver updated to include all models within the same driver package. Updated manuals available on the IP-Parallel-IO product page. The hardware is available in 7
10/2009 New Product Announcement PCIeBiSerialDb37 design has been released. New member of industry leading BiSerial family. PCIe 1-4 lane version with 18 differential IO, DMA, Memory, programmable interrupts, terminations and plenty of room for complex state-machines. Initial implementation
6/2009 New Product Announcement PCI-ASCB design has been released. Implements 2 redundant channels of ASCB with standard pinout DB9 connectors mounted through PC rear bezel. Location for PMC or prPMC for local SW processing of ASCB data. Locations for optional FIFO´s. Windows® support.
5/2009 New Product Version Announcement PMC BiSerial III BA19 design has been released.
4/2009 New Product Announcement ccPMC-HOTLink design has been released. Multiple HOTLink channels per conduction cooled PMC with RS-485 for a secondary low speed control bus. Each channel with independent DMA support. Programmable frequency operation. Transformer or direct coupled RX. LVDS or RS485 options for secondary bus. PECL on HOTLink channels. PLL support for HOTLink transmit control.
3/2009 New Product ccPMC-SpaceWire SpaceWire has been ported to the ccPMC platform. 4 independent channels per card each with DMA, Memory and Time Code support. Option for Radiation Hardened FLASH memory. Optional Larger FIFO´s. Windows® and Linux drivers plus reference application software available. Cables, SpaceWire specific debugging / breakout, cable to connector adapters and other interface support.
2/2009 New Product Enhancement: Customerized version ccPMC-Parallel-TTL design has been updated with a user specific version. The
2/2009 New Product Enhancement: Customerized version ccPMC-Parallel-TTL design has been updated with a user specific version. The
11/2008 New Product PC104p-SpaceWire SpaceWire has been ported to the PC104p and PCI-104 platforms. 4 independent channels per card each with DMA, Memory and Time Code support. Optional Larger FIFO´s. Windows® and Linux drivers plus reference application software available. Cables, SpaceWire specific debugging / breakout, cable to connector adapters and other interface support.
11/2008 New Product Enhancement: Customerized version The PMC-Parallel-TTL design has been updated with a user specific version. The
9/2008 New Product Enhancement: Customerized version The PMC-Parallel-TTL design has been updated with a user specific version. The
8/2008 New Product Enhancement: Linux Driver Utilize SpaceWire to communicate with the European Space Agency, and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a hierarchical point-to-point system with high speed paths. Dynamic Engineering supports SpaceWire with PMC, and PCI based hardware along with Windows® and Linux drivers. Cables and other hardware including the SpaceWire link tester
The SpaceWire driver includes
When the Base module is installed, it interfaces with the PCI system configuration utility to acquire the memory and interrupt resources for each device installed. A SpaceWire
In this way each of the channels on the SpaceWire card can be treated separately for easy to write user level software. For example, large DMA transfers can be initiated without the software doing any arbitration between the channels as separate DMA engines are provided per RX and TX channel. The number of interrupts to handle can be drastically reduced with the channelized architecture.
The SpaceWire Linux driver comes with example test software that can perform DMA tests on the internal memory of the SpaceWire device or external loop-back testing between the ports. The driver handles the details including programming the PLL.
7/2008 New hires Dynamic Engineering has hired Nicola Leisses to work in the marketing and special projects group. Nicola is a recent graduate from the University of Santa Clara. Nicola graduated Magna Cum Laude with a BS degree from the Leavy School of Business.
6/2008 New and improved Product Enhancement: Updated, redesigned Linux base driver for PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, and PC104p4IP carriers is done. The first child driver to go with the carrier drivers is for IP-QuadUART, and is now completed. The carrier driver comes with a
6/2008 New Product Announcements: PCIeBPMCX1 and PCIeBPMC
The PMC carrier family has been updated to include two new PCI Express based single PMC carriers using the TSI384. The PMC side of the bridge is programmable bus speed and width. The X1 version supports true PCI-X speed at the PMC with 4 lane PCIe operation. The PCIeBPMC uses only 1 lane to provide 32/33 capability to the numerous single slot options in new PC´s. Pn4 is routed to a SCSI connector with matched length differential routing and 100 ohm impedance. The design features an efficient built-in power supply, options for "Zero Slot Fans"™, Lane and Power status LED´s. Both versions are immediately available from stock.
5/2008 New and improved Product Enhancement: Updated, redesigned Linux base driver for PCI3IP, PCI5IP carriers is done. Now porting to cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP. First IP level driver is for the IP-QuadUART. Generic driver included with carrier driver allows any IP to be used with the carrier.
4/2008 New Product Enhancement: cPCI Receiver Controller
The cPCI Receiver Controller is a 3U 4HP design that can be used for many purposes. The primary design implementation is to act as the controller slice within a digital receiver. The host computer can access the Receiver Controller over the PCI bus within the cPCI system. The Receiver Controller buffers commands from the host and converts them to the appropriate format to interface with the rest of the Digital Receiver. The initial design is controlled with several SPI [Serial Peripheral Interface] buses. In addition A/D, D/A, Temperature sensor, UART, Clock references are supported.
Available now.
3/2008 New Product Enhancement: IP-CAN
Talk to your car or other CAN device, snoop a bus or be an active participant. IP-CAN is a versitile design that has been updated for better logistical support. IP-CAN has been adapted to add software selectable termination options. Using calls from the new IP-CAN driver for Windows® the user can configure the termination to match end-of-bus or mid-bus topologies without physically changing the hardware. The driver supports IP-CAN on all Dynamic Engineering IP carriers. The driver and hardware have been tested at high and low frequencies over long and short cables with multiple nodes. The driver supports the Pelican and standard modes of operation. Multiple IP-CAN boards can be used in the same system.
Available now.
1/2008 New Product Announcement: PCI-Harpoon
PCI-Harpoon can be used for simulation, control, command and other embedded IO functions. The
Available now.
10/2007 Product Update Announcement: cPCI4IP
The cPCI based IndustryPack® Carrier with 4 slots has been updated to provide a
Available now.
10/2007 Product Update Announcement: PMC-SpaceWire and PCI-SpaceWire
The Industry standard PMC and PCI SpaceWire designs have been updated to include an option for deep FIFOs on channel 0. 512K organized as 128K x 32 is available to support TX and RX on channel 0. Add
Available now.
9/2007 New Product Announcement: PMC-BiSerial-III-TRANS
The Industry leading PMC BiSerial III is now available in a Conduction Cooled, Transformer Coupled configuration. The IO are transformer coupled RS-485 and support up to 40 MHz. The IO is matched length differentially routed to Pn4. Extended temperature operation is standard. Conformal coating is an option. The first customer design is complete with the
Available now.
9/2007 New Product Announcement: PMC-Parallel-TTL
Most systems need TTL lines and in some cases a lot of them. The PMC Parallel TTL packs 64 TTL IO with Change Of State
Available now.
8/2007 New Product Announcement: Dynamic Engineering rugged chassis PCI-104, PC/104p and PC104 applications
Rugged chassis with built in heat sink, mounting flange, gaskets, and an internal shock mounted card cage. Chassis is available in multiple lengths.
Press Release
6/2007 New Product Announcement: Dynamic Engineering Power Supply for PCI-104, PC/104p and PC104 applications
Create +5V, +3.3V, -12V and -5V from a 12V input - wall mount transformer, battery or similar. 8A on the +5 and +3.3V rails, 4A on the -12 and -5V rails max. +12V routed through and fused at 4A to stack. High efficiency switcher designs with fused filtered power output. Delayed turn-on to minimized inrush current. Works with any PCI-104, PC104, or PC104p stack.
5/2007 New Product Announcement: PMC-BiSerial-III-LM6
Two serial protocols with test ports plus direct and DMA support. Customerized version of PMC-BiSerial-III design with VHDL and Windows® driver modified for this effort. Dynamic Engineering features custom upgrades to the
3/2007 We moved: Dynamic Engineering has relocated to a new larger facility located at 150 Dubois Street, Suite #3, Santa Cruz, Ca. 95060. The new facility features advanced manufacturing capabilites to allow both standard and ROHS processing to occur, on-site support for our clients, more storage for shorter lead times, and creative space to help expand our Dynamic Designs
2/2007 New Product Announcement: Dynamic Engineering IP-1553 1 and 2 channel Dual Redundant Mil-STD-1553
By customer request Dynamic Engineering has developed a 1553 interface on an IndustryPack® format card. The ACE industry standard interface is compatible with the current and previous versions of 1553. Speeds up to 1 MHz. Multiple programmable interface modes. Direct or transformer coupled interface is shunt programmable.
1/2007 New Product Announcement: PCIBPMCX1
The PMC carrier family has been updated to include a single PMC carrier using the Intel 31154 PCI/PCI-X bridge. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The Pn4 connector is routed to a SCSI connector with matched length differential routing and 100 ohm impedance.
1/2007 IP Crypto: Dynamic Engineering IP-Crypto
By customer request Dynamic Engineering has conformal coated and temperature tested 10 units. The IP-Crypto units were installed onto multiple PCI3IP carriers and loaded into a temperature chamber. The units were cycled from -30C to +80C with 2 hour dwell times at each extreme for 6 cycles powered off. The IP-Crypto´s were then tested - running the Dynamic Engineering carrier driver with IP-Crypto driver module over a range of 0C to 50C with 2 hour dwells for 4 cycles. All units passed all tests first time through.
11/2006 New Product Announcement: Dynamic Engineering IP-CAN Dual Channel Controller Area Network card
By customer request Dynamic Engineering has developed a dual CAN interface on an IndustryPack® format card. The SJA1000 / SJA1041 industry standard interface is compatible with the current and previous versions of CAN. Speeds up to 1 MHz. Multiple programmable interface modes. Direct or isolated interface.
10/2006 New Product Announcement: Dynamic Engineering Extended Temperature 6U cPCI Dual PMC Carrier
By customer request Dynamic Engineering has developed a dual PMC extended temperature version of the popular cPCIBPMC design. The design effort included switching to a new bridge to meet the temperature and timing requirements. The new bridge brings new features including the ability to operate the PMC side at a higher clock rate than the cPCI side. The new bridge also has built in features for local address spaces, using the PMC in monarch mode, and operating in transparent or non-transparent modes. The design is ready for your cPCI PMC applications. Please contact Dynamic Engineering with your custom requirements.
8/2006 New Product Announcement: Dynamic Engineering Extended Temperature 3U cPCI PMC Carrier
By customer request Dynamic Engineering has developed an extended temperature version of the popular cPCIBPMC design. The design effort included switching to a new bridge to meet the temperature and timing requirements. The new bridge brings new features including the ability to operate the PMC side at a higher clock rate than the cPCI side. The new bridge also has built in features for local address spaces, using the PMC in monarch mode for the secondary side, and operating in transparent or non-transparent modes. The design is ready for all of your PMC applications. Please contact Dynamic Engineering with your custom requirements.
8/2006 New Product Announcement: Dynamic Engineering SpaceWire Connector Board "DESWCB"
The DESWCB is used to interface custom cables to SpaceWire cables. Up to 28 SpaceWire connectors / cables can adapted to your custom cable per DESWCB. Please contact Dynamic Engineering with your custom requirements.
8/2006 New Version Announcement: IP-BiSerial-BA13
The IP-BiSerial-BA13 has been released. The new version of the IP-BiSerial-IO is available with programmable 16 or 32 bit serial data, programmable parity. programmable Transmit clock rate. Wide range of receive rates, 2K of FIFO per channel. One transmitter and one receiver per board. Please contact Dynamic Engineering with your custom requirements.
7/2006 New Product Announcement: PC104p-BiSerial-III-TG1
The PC104p-Biserial-III-TG1 has been released. The buoy based hardware will read sensors located within the buoy to allow the data to be recorded and processed. Four independent DMA based receive channels per card. 3 wire interface using RS-485 compatible hardware. An additional transmit channel is supplied for loop-back. Please contact Dynamic Engineering with your custom requirements.
7/2006 New Product Announcement: PC104p-BiSerial-III-BA14
The PC104p-Biserial-III-BA14 has been released. The BA14 interface has UART like features with a serial rate of 6.25 MHz, start, stop, marking states, and 16 bit data preceded by a Command / Data indicator. The transmit and receive channels are independent and supported by DMA. Please contact Dynamic Engineering for your custom version.
7/2006 New Product Announcement: PMC-Wizard
The PMC-Wizard is intended for use in ultra high-speed bidirectional point-to-point data transmission systems. The primary application is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 Ω. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media, and the noise coupling to the environment. The PMC-Wizard can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit / receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, twisted pair, or an optical link. Data is then reconstructed into its original parallel format. Significant power and cost savings are realized when compared with parallel solutions. PMC-Wizard is provided with independent DMA support for each input and output channel. Windows® driver available.
6/2006 New Product Announcement: PC104p-BiSerial-III
The PC104p family has been updated with a new member of the BiSerial family. The updated BiSerial-III features a Spartan III 1500 FPGA, 16 transceivers (RS485 or LVDS), 8 bit TTL port, (4) DAC, (4)ADC, PLL. The PCI interface has been updated to work with DMA. Each IO channel can have a separate DMA channel to allow multiple data streams to be handled with very low overhead from the CPU. The first application will be installed in a buoy. What do you need? Please contact Dynamic Engineering for your custom version.
3/2006 New Product Announcement: PMC-XM
The PMC family has been updated to include a user programmable Virtex based mezzanine capable PMC design. The PMC-XM has a "fixed" FPGA which handles the PCI bus including a 4 channel DMA function and a user programmable Virtex SX35 device. The Virtex is supported with a PLL, RAM, and a mezzanine position. The design is in final integration.
2/2006 New Product Announcement: PMC-MC-X2
The PMC carrier family has been updated to include a Dual PMC carrier. The PMCs are installed on both front and rear surfaces for a dense packaging solution. 64/66 and 32/33 operation is supported. It is anticipated that a PrPMC is installed into slot 0. On board clock distribution, interrupt routing, and bus arbitration. A single 12V power supply [wall transformer] is used along with the internal power supplies to power the +5, +3, and +/ 12V rails. VIO is programmable. "1/2 size version of X4"
1/2006 New Product Announcement: PMC-MC-X4
The PMC carrier family has been updated to include a Quad PMC carrier. The PMCs are installed on both front and rear surfaces for a dense packaging solution. 64/66 and 32/33 operation is supported. It is anticipated that a PrPMC is installed into slot 0. On board clock distribution, interrupt routing, and bus arbitration. A single 12V power supply [wall transformer] is used along with the internal power supplies to power the +5, +3, and +/ 12V rails. VIO is programmable.
12/2005 New Product Announcement: cPCIBPMC3U64-ET
The PMC carrier family has been updated to include an Extended Temperature version of the popular cPCIBPMC 3U carrier. The extended temperature version will support -40 to +85 C operation with 64/66 or 32/33
11/2005 New Product Announcement: PCI SpaceWire
Dynamic Engineering has won a contract to port the popular PMC SpaceWire design onto the PCI format. The PCI SpaceWire will have 4 channels supported through the PCI Bezel on standard micro D connectors. The PCI SpaceWire will be completely compatible with the PMC-SpaceWire, and eliminate the need for a carrier in PCI systems. It is anticipated that the design will be available for delivery in early May 2006.
10/2005 New Product Announcement: PCIBPMCx2
The PMC carrier family has been updated to include a dual PMC carrier using the Intel 31154 PCI/PCI-X bridge. One PCI slot provides two PMC positions. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The seconday side can be hidden from the primary side to support PrPMC applications. For example: use the main PCI bus to load software into the PrPMC, then use the hidden mode to communicate between the PrPMC, and a second IO based PMC. Ideal for embedded applications with high speed local processing without depency on the main PCI bus timing.
9/2005 Product Update: IP-OptoISO-16
The IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FETs. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. The IP-OptoISO-16 has been enhanced with the D and S side now available at the IO connector to allow high and low side switching. Each switch is independent for mixed mode operation. As of 9/12/05 all new orders will receive revision C . The new design is compatible with the previous revisions.
The FETs switch the Drain and Source. The Drain or Source for each switch is tied to a reference voltage. When the switches are closed the S is connected to D. The voltage range is 0-60 VDC. Each switch can handle 1.5A. The traces on the IP are rated for 1.5A. Please check with your IP carrier for maximum current capabilities. Please contact Dynamic Engineering if you need a carrier with power traces.
8/2005 New Product Announcement: PMC-BiSerial-III
The PMC BiSerial family has been updated to include a Spartan III [Xilinx] based card with expanded capabilities.. Building on the knowledge and experience gathered from multiple IP and PMC BiSerial implementations and adding in the latest technology has created the PMC-BiSerial-III. The BiSerial III features completely isolated FIFOs with 32 bit ports for increased adaptability and performance. The [34] RS-485 / LVDS buffers have programmable termination, and direction control. Half-Duplex, Full-Duplex and single ended systems can be configured with software and VHDL. The denser, faster FPGA will implement the most complex state-machines. The prototype fabs are in test for the initial customer specific version; 32 Manchester channels with independent memories in one PMC.
7/2005 New Product Update: PMC-SpaceWire
Dynamic Engineering has delivered the first version of PMC-SpaceWire to three customers. The initial fab lot has been depleted. The design is being updated for ROHS and incorporation of design updates. The updated revision will be available late August / early September 2005. PMC-SpaceWire implements SpaceWire in a convenient PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS signaling and a 9 pin MDM connector. PMC-SpaceWire provides 4 SpaceWire attachments allowing your host to directly communicate with multiple devices. The hardware is supported with a Windows® driver. PMC-SpaceWire has been tested at 200 MHz. Test cables have been developed to meet the base requirements of SpaceWire - a good combination of capabilities and lower cost.
6/2005 Product Update Announcement: ROHS compliance
Dynamic Engineering has a plan in place to meet the ROHS requirements by the 2006 implementation deadline. Dynamic Engineering has decided to go with Gold instead of Tin for superior performance in the short and long term life of our product. Many of the components that we use already meet the ROHS requirements. When the rest of the components become available we will switch our process over to use ROHS compliant solder paste etc.
5/2005 New Product Announcement: PC/104p-BaseBoard
The BaseBoard is part of the PC/104 Module family of modular I/O components by Dynamic Engineering. The BaseBoard is used to integrate a PC/104p stack with the power supply, 35 Optocoupled Inputs, 37 Optocoupled Outputs, 2 UART - RS-485 ports, 2 ARINC 429 - TX/RX, 4 ADC Ports, and 4 DAC Ports comprize the onboard feature set of the BaseBoard design. The Right hand PC/104 slot is designed to be occupied by the Power Supply module which accepts 28V and supplies the standard PC/104 voltages on the ISA connector. The left hand slot is used to add a PC/104p stack.
4/2005 New Version Announcement: PMC-Serial-M1
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provide four RS-422 UART channels and no SCC
The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating frequencies. Dynamic Engineering performed the design to support Mitre. The hardware is supported with an engineering kit.
4/2005 New Product Update: PMC-SpaceWire
Dynamic Engineering is under contract to make the first customerized version of PMC-SpaceWire. PMC-SpaceWire implements SpaceWire in a convenient PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS signaling and a 9 pin MDM connector. PMC-SpaceWire provides 4 SpaceWire attachments allowing your host to directly communicate with multiple devices. The hardware is supported with a Windows®; driver. PMC-SpaceWire has been tested at 200 MHz. PMC-SpaceWire is in final integration with customer equipment with first deliveries expected in the start of May/2005. Test cables have been developed to meet the base requirements of SpaceWire - a good combination of capabilities and lower cost.
3/2005 New Product Announcement: BaseBoard
Dynamic Engineering is under contract with BAE to develop a specialized PC/104p ³BaseBoard². The BaseBoard will have two PC/104 positions allowing a power supply module to be installed in one and a PC/104p stack to be installed in the other. The BaseBoard acts as stack position 0 utilizing a Xilinx FPGA to interface with the PCI bus. BaseBoard has Optocoupled IO, UARTs, ARINC 429 ports, DAC and ADC ports. This is a quick turn project with delivery expected the first week of May 2005.
2/2005 New Product Announcement: cPCIBPMC3U64
Dynamic Engineering has completed the cPCIBPMC3U64 design. The Compact PCI carrier provides 1 PMC position on a 3U 4HP cPCI card. The configuration is intended for 64 bit cPCI backplanes. The bridge provides isolation from the backplane allowing for 3.3 or 5V PMCs to be installed and to make adjustments in clock speeds. VIO is jumper selectable on the PMC side of the Bridge. There are options for connecting the Ethernet, Serial and I2C ports. IO is through the cPCI bezel.
Another version is coming soon which will have a 32 bit PCI bus and user IO to the rear panel.
1/2005 New Version Announcement: PMC-Serial-RTN5
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provide an option for RS-232 operation with the Serial Communications Controller, plsu 2 RS-232 and 2- RS422 channels on the UART.
The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating frequencies. Dynamic Engineering performed the design to support Raytheon and the US Coast Guard. The hardware is supported with an engineering kit. A Windows driver is being written for the PMC-Serial-RTN5
12/2004 Updated Product Announcement: PCI-NECL-ASN1
The PCI-NECL-ASN1 supplies 20 ECL transmitters and 20 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. The 20 inputs and outputs can be programmed to make parallel and serial interfaces. The spare IO can be used as a parallel port. PCI-NECL-ASN1 is a customerized version of the PCI-ECL card. Dynamic Engineering performed the design to a parallel interface. The hardware is supported with a Windows¨ driver. The driver and design are available as part of the engineering kit to allow customers to create their own custom interfaces. The on-board FLASH is reprogrammable to support custom requirements.
11/2004 Driver available: PMC Parallel IO
The PMC Parallel IO is now supported by a Windows® 2000/XP Compatible driver. The driver will decrease your time to market with direct access to the PMC Parallel IO hardware using standard C/C++ calls.
The PMC Parallel IO provides the common requirement of single ended IO for embedded systems. Each of the 64 IO are independently programmable for input and output. Front and rear panel IO are available. Interrupts are supported. Custom IO requirements are supported with a reprogrammable FPGA device.
10/2004 updated Design: PCI_Altera_485/LVDS
The PCI-Altera-485/LVDS has been updated to have the option to use a FLASH based PROM to load the Altera at power-up or to load from the Xilinx via software and the PCI bus. For applications requiring a quick start the PROM can configure the Altera before the OS is running. The PCI-Altera provides reconfigurable logic with a 20K400E plus DMA, 16 FIFOs, 8 triple PLLs, 12 TTL IO, and 40 RS-485 or LVDS IO.
10/2004 New Version Announcement: IP-HaveQuick is a new version of the IP-Parallel-HV
The HaveQuick version provides master and target capability to interface with TOD [time of day] equipment using the HaveQuick manchester encoded interface standard. As a target the time code from the TOD unit can be read by the host for an accurate time. The seconds, minutes, hours, days and years are encoded into the format. The IP-HaveQuick locally interpolates to provide a higher resolution time synchronized to the 1PPS [one pulse per second] reference and time code data. As a Master the hardware can be programmed with the start time and then run independently to provide a reference. The hardware is supported with an IP driver compatible with the Windows 2000® and XP® OS.
10/2004 New Version Announcement: PMC-BiSerial II-PS2 is a new version of the PMC-BiSerial II
The PS2 version provides eight serial channels and an 8 bit parallel port with RS-422/485 IO. The serial channels are configured with 4 transmit and 4 receive. The protocol provides a Data, Clock and Strobe interface. The transmit rate is programmable up to 20 MHz. Each channel [8] has a 128 x 32 FIFO for data storage. Lower cost version of the standard PMC-BiSerial product with smaller Block RAM FIFOs and more channels.
9/2004 New Product Announcement: cPCI4IP
The cPCI4IP provides four IndustryPack® slots in one 6U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in each slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. Windows® driver available.
9/2004 Updated Product Announcement: cPCI2IP
The cPCI2IP provides two IndustryPack® slots in one 3U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The updated design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in either slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. Windows® driver available.
9/2004 New Version Announcement: PMC-Serial-RTN4
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provde an option for RS-232 operation with the Serial Communications Controller.
The L3 version is available with RS-485 IO on the SCC.
Both models have RS-232 IO for the QuadUART. The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating frequencies. Dynamic Engineering performed the design to support Raytheon and the US Coast Guard. The hardware is supported with an engineering kit.
8/2004 New Product Announcement: PCI-NECL-ASN1
The PCI-NECL-ASN1 supplies 20 ECL transmitters and 20 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. PCI-NECL-ASN1 is a customerized version of the PCI-ECL card. The Interface has 16 bit parallel data with reference clock, data valid, data ready, and buffer limit handshaking. Dynamic Engineering performed the design to support Asine Ltd. The hardware is supported with a Windows¨ driver.
8/2004 New Product Announcement: PCI-NECL-XG1
The PCI-NECL-XG1 supplies 19 ECL transmitters and 19 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. The 19 inputs and outputs can be programmed to make parallel and serial interfaces. The spare IO can be used as a parallel port. PCI-NECL-XG1 is a customerized version of the PCI-ECL card. Dynamic Engineering performed the design to support XG Technologies for a digital receiver interface which operates at 170.6 MHz.. The interface is a 3 wire serial implementation leaving 2 - 16 bit parallel ports. The hardware is supported with a Windows¨ driver.
7/2004 New Product Announcement: PMC-SpaceWire
Dynamic Engineering is under contract to make the first customerized version of PMC-SpaceWire. PMC-SpaceWire implements SpaceWire in a convenient PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS signaling and a 9 pin MDM connector. PMC-SpaceWire provides 3 SpaceWire attachements allowing your host to directly communicate with multiple devices. The hardware is supported with a Windows¨ driver.
6/2004 New Product Announcement: PCI-Serial_ECL
The PCI-Serial-ECL supplies 19 ECL transmitters and 19 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. The 19 inputs and outputs can be programmed to make parallel and serial interfaces. The spare IO can be used as a parallel port. Dynamic Engineering is under contract to make the first customerized version of the PCI-Serial-ECL for a digital receiver interface which operates at 170 MHz.. The interface is a 3 wire serial implementation leaving 2 - 16 bit parallel ports. The hardware is supported with a Windows¨ driver.
6/2004 New Product Announcement: PC/104p-BiSerial
The BiSerial family has been expanded to include a PC/104p version of the design. The new implementation builds on the PMC-BiSerial-II and IP-BiSerial adding ADC and DAC capabilities. High speed programmable FPGA for application specific state-machine implementations. 16 RS-485 transceivers which can be swapped with LVDS IO, 4 ADC [16 bit, 200 KHz.] , 16 DAC [16 bit, 200 KHz] and 8 TTL make up the IO. Use for memory buffered communications and control, hardware interface simulation, command and control etc. BiSerial designs have been used for industrial control, test support, simulation of other equipment, "glue" between incompatible systems, communications, and more. Dynamic Engineering is under contract to make the first customerized version of the PC/104p-BiSerial for a LASER interface. The hardware is supported with a Windows¨ driver.
5/2004 Product Update Announcement: PCI5IP-XP/2000
PCI5IP-XP/2000 is now available to support the Windows¨2000 OS. The PCI5IP-XP/2000 driver is a "Parent" Driver for Windows¨XP or Windows¨2000 systems. The driver facilitates the integration of up to 5 IP modules per PCI5IP and up to 10 PCI5IPs per system providing the kind of flexibility that system designers need in todays fast changing high tech market place. The driver is a purchase once and use many item - no additional royalties etc. for same company use. The Driver and PCI5IP are stocked items.
3/2004 Product Update Announcement: PCI-Altera-485/LVDS
The PCI-Altera-485 has been updated to have a build option to install LVDS transceivers creating the PCI-Altera-LVDS. There are 40 transceivers on the card and the transceivers can be implemented with 485, LVDS or mixed. The 485 transceivers are rated for 40 MHz operation. The LVDS transceivers are rated for 200 MHz operation. In addition the PCI-Altera Windows¨ driver has been updated to support XP and 2000. The PCI-Altera is designed to accept user VHDL files and the generic driver allows the user to communicate with their custom implementation using standard C. Easy to install, easy to load, easy to use.
2/2004 New Product Announcement: PCI Cable adapter to support IP-Crypto and IP-Tape
The Cable Assembly Crypto/Tape interconnects the IP Module Carrier and the PCI Bezel via a connector board and and internal ribbon cables. The IP-Crypto is broken out to an RJ45 and the IP-Tape to a SCSI connector. The IP-Tape connector has additional pins for"self-healing" fused power and ground.
2/2004 New Product Announcement: Single Slot IP Module carrier for PC/104p applications
The PC104pIP lets you mount a an industrypack¨ module onto a PC/104p in a standard PC/104p slot. The PC104pIP is based on the PC104p4IP design and features 8/32 MHz IP clock selection, fused filtered power, watchdog timer, 32 bit data handling, little/big endian support and more.
1/2004 New Design: PCI <-> PC/104p adapter
The PCI2PC104p lets you mount a PC/104p devide in a standard PCI slot. The PCI2PC104p has two configurations to support production and test. Testpoints are provided for the PCI signals in the test configuration.
1/2004 New Design: Cable adapter
The IP-Crypto and IP-Tape are now supported with a cable adapter. The cable adapter converts from ribbon cable [2 x 50] to RJ-435 and SCSI III connectors. The RJ-45 has the IP-Crypto interface and the SCSI III connector has 1:1 from the ribbon plus additional fused power and ground. The SCSI connector can be used to support any IP.
1/2004 New Design: Windows¨XP and 2000 drivers for the IP Crypto.
The IP-Crypto drivers are "Child" Drivers used with a "Parent" driver for the carrier the IP-Crypto is mounted to. For example with the PCI3IP the IP-Crypto can be installed into a standard PCI slot and controlled with standard C software and Windows¨2000 or XP operating systems. The IP-Crypto driver comes with source, example calling program and documentation.
12/2003 New Design: PCI_Altera_485_XP
The PCI-Altera-485-XP driver is a "Parent" Driver for Windows¨XP systems. The driver facilitates the operation of the PCI-Altera-485. Multiple PCI-Altera-485's are supported per system providing the kind of flexibility that system designers need in todays fast changing high tech market place. The PCI-Altera-485 driver comes complete. The base driver provides functionality to load the Altera with the user design, recognize different Altera implementations and load the appropriate child driver, and manage the PCI side of the design . The reference design [VHDL and load file] provided with the driver supports the basic features on the PCI-Altera-485 - PLLs, FIFOs etc.
11/2003 New Design: PMC-Serial
The PMC-Serial is an upgrade and replacement for the PMC-4U. The PMC-Serial features up to 8 UART channels, an SCC, RS485, RS232, RS188, RS423 options for IO. The standard configuration has 4 UART channels and 2 SCC channels. The UART is supported with 128 Deep FIFO per channel and performance logic for effecient operation on the PCI bus.
11/2003 New Design: IP-BiSerial-Miller
The IP-BiSerial-MLR is what you need to connect your system to a "Miller" encoded source and to transmit to another "Miller" encoded device. The design features 16K bytes FIFOs, programmable interface rates, programmable sync pattern, programmable frame length, programmable interrupts and more. Miller encoding provides a 50% duty cycle [overall] data with embedded clock interface. The encoding technique utilizes the time between transitions to define the data. Ideal for telemetry and fiber applications. A Windows¨XP driver is available.
10/2003 New Design: PCI3IP-XP
The PCI3IP-XP driver is a "Parent" Driver for Windows¨XP systems. The driver facilitates the integration of up to 3 IP modules per PCI3IP and up to 10 PCI3IPs per system providing the kind of flexibility that system designers need in todays fast changing high tech market place. The PCI3IP-XP driver comes complete with a generic IP driver to allow the use of IndustryPack¨ Modules that do not have an IP driver designed.
10/2003 Updated Design: PMC2PCI
The PMC2PCI by Dynamic Engineering integrates A PCI slot into a PMC environment. Use your favorite PCI card with a PMC carrier. 32/33 and 64/66 operation. 3.3 or 5V IO. Now with a more efficient switching 3.3V power supply design. User shunt to select PMC 3.3 or regulated 3.3. Please look at the data page for a complete description.
9/2003 New Design: PC104p4IP
The PC104p4IP by Dynamic Engineering integrates your favorite IndustryPacks with the PC/104+ module system. 4 IPs can be mounted to a single PC/104 slice. Fused filtered power on each slot, 8/16/32 bit operation with 16 and 32 bit IP modules, independent 8/32 MHz selection and more. Please look at the data page for a complete description.
5/2003 New Design: IP-Pulse
The IP-Pulse by Dynamic Engineering solves your programmable pulse generation requirements with 4 channels in a single IP Module. Each channel is independent and can be programmed with the pulse width and time between pulses. nS to seconds. The output pulses can be sent continuously or for a pre-programmed count. The four channels can be synchronized or started independently. Interrupt or polled operation.
5/2003 Updated Design: PCI3IP
PCI3IP-XP and Linux drivers coming soon! The PCI3IP by Dynamic Engineering has been updated with an alternate user interface. The PCI3IP initializes into the unifed (legacy) register set to support current installations. The distributed register set is selected with a control bit in the base register. The additional features will allow drivers written for the PCI5IP to be ported to the PCI3IP and vice-versa.
5/2003 New Design: PCI5IP-XP
The PCI5IP-XP driver is a "Parent" Driver for Windows¨XP systems. The driver facilitates the integration of up to 5 IP modules per PCI5IP and up to 10 PCI5IPs per system providing the kind of flexibility that system designers need in todays fast changing high tech market place.
5/2003 New Design: IP-BiSerial-NG4
Software programmable 3/4 wire modes, parity, transmit frequency, the width of the synchronization pulse, the time delay after the sync and the start of data, and the time between data words. The word transfer has an associated Word Sync signal to provide for framing and error checking. The Frame sync signal provides for message level synchronization. The Ng4 has programmable receive word count and receive all mode. The IP BiSerial NG4 has a 50 MHz reference oscillator.
4/2003 New Design: cPCI2PMC
The cPCI2PMC ( cPCI to PMC ) cPCI2PMC adapter / carrier converter card provides the ability to install a PMC card into a standard cPCI slot. The cPCI2PMC has a PMC card slot mounted to a universal 3U 4HP cPCI card. Suitable for 32/64 with 33/ 66 MHz bus operation. The PMC user IO connector Pn4 is optionally connected to J2 for rear panel IO. The PMC bezel connector is mounted though the cPCI mounting bracket.
4/2003 New Design: cPCI2IP
The cPCI [CompactPCI] compatible cPCI2IP cPCI2IP design adds 2 Industrypack compatible slots to your cPCI host. The cPCI2IP acts as an adapter, converter, carrier, or bridge between the cPCI bus and your IndustryPack hardware. The cPCI2IP is a 3U 4HP cPCI design with 2 IP slots.
3/2003 New version: IP-BiSerial-Q1
New version of the IP-BiSerial-IO designated IP-BiSerial-Q1 completed for QinetiQ The IP-BiSerial-Q1 features 16 or 32 bit programmable data length plus parity, bursted clock with frequency options and RS422 [RS485] IO.
3/2003 Updated Design: PCI3IP
The PCI3IP is now updated to be PCI 2.2 compliant and PCI universal voltage. The updated version is a drop in replacement for the previous PCI3IP revision. The PCI3IP features FAST¨ technology for high performance accessing your IndustryPack¨ modules.
2/2003 New Design: IP-OptoISO-16
16 Optically Isolated 0-60V 1.5A outputs - IndustryPack Product now available for ordering. Please e-mail sales@dyneng.com
1/2003 Design Award: IP-OptoISO-16
16 Optically Isolated 0-60V 1.5A outputs - IndustryPack Module design awarded to Dynamic Engineering. Product available for shipping March 1, 2003. Please e-mail sales@dyneng.com
1/2003 Developments: IP-OctalSerial
8 Channel Serial Data Interface IP Module shipped to customer. Please e-mail sales@dyneng.com
1/2003 Developments: IP-QuadUart-485
Customized version of the IP Quad UART ships to customer. Please e-mail sales@dyneng.com
8/2002 Contract Award: PMC-0C12
L3 Communications has awarded an new development contract to Dynamic Engineering to create the PMC-OC12. The PMC-OC12 development will be a quick reaction program to provide an OC12 capable fiber interface on a PMC format card. The Agere "Ultramapper" will be utilized to provide the protocol processing.
8/2002 -NG2 ships: IP-BiSerial-NG2
The IP-BiSerial update to create the IP-BiSerial-NG2 has been completed and the hardware shipped.
7/2002 -S311 ships: PMC-BiSerial
The PMC-BiSerial-S311 Shipped to the customer and is now in integration at their facility. The PMC-BiSerial-S311 was delivered with an NT driver and PCI adapter to allow Northrop Grumman to interface to legacy radar systems from a standard PC.
7/2002 Contract Award: PMC-BiSerial
BAE Systems has awarded an upgrade contract to Dynamic Engineering to create the PMC-BiSerial-BAE1. The PMC-BiSerial-BAE1 will feature a synchronous serial differential interface to a combination time distribution network and control data. Independent transmit and receive channels.
7/2002 Contract Award: IP-BiSerial
Northrop Grumman Corp. has awarded an upgrade contract to Dynamic Engineering to create the IP-BiSerial-NG2. The IP-BiSerial-NG2 will feature a standard satelite interface [Frame Sync, Word Sync, Data and clock]. Independent transmit and receive channels. Programmable parity, length, and data rates.
6/2002 Contract Award: PMC-BiSerial
Northrop Grumman Corp. has awarded an upgrade contract to Dynamic Engineering to create the PMC-BiSerial-S311. The PMC-BiSerial-S311 will be used with a PCI2PMC and Windows NT driver to provide an S311 interface within a PCI chassis.
6/2002 Developments: PCI_Altera_485
Program your own Altera 10K200E or 10K130E from the PCI bus. 40 - 20 MHz. RS-485 IO and 12 TTL IO are provided via D100 connector for IO. Spartan II and PLX 9054 provided to manage DMA on PCI bus. 16 - 4K x 8 FIFOs between Altera and Xilinx. One 1K x 32 FIFO provided for DMA optimization. Status - Schematic complete. Placement complete. Routing in progress. ETA - July 2002. Boards will be supplied with base Altera implementation, NT compatible loader software [for Altera] and preprogrammed Xilinx.
5/2002 Developments: PCI3IP
PCI - Industrypack adapter - updated to have an optional minimized memory map. The memory space was decreased to match the ID, IO, and INT memory requirement. Only 2K bytes requried on the PCI bus. Prior purchased hardware can be upgraded with our PROM upgrade program. Please e-mail sales@dyneng.com .
4/2002 Developments: IP-QuadUART
The IP-QuadUART provides 4 UART channels on a single IP card. The channels are supported by 128 byte FIFOs and programmable RS-232 / RS-422 IO. Multiple baud rates are supported up to 2 MHz.
3/2002 Developments: PCI3IP
PCI - Industrypack adapter - updated to include new static and dynamic address 32 <=> 16 bit data conversion [PCI <=> IP]. Prior purchased hardware can be upgraded with our PROM upgrade program. Please e-mail sales@dyneng.com .
2/2002 Developments: PCI5IP
PCI - Industrypack adapter - Use a PCI card slot to mount your time tested IP module designs. 5 IPs in one slot. 8/32 MHz selectable per slot. Release date 3/15/02
1/2002 Developments: PMC2PCI
PMC - PCI adapter - Use a PCI card for development or production in a PMC slot. Save time and money with existing PCI cards when a PMC version is not available. In Stock
1/2002 Contract award: Embedded PC design: for special data processing application. P3 with SDRAM, FLASH, Ethernet, local PCI, and Xilinx based data filtering and control functions.
1/2002 Developments: pciBpmc
PCI Bridge PMC adapter - All of the benefits of our PCI2PMC design plus a PCI bridge to allow multiple PMC's to be installed per PCI bus segment. On board 7A 3.3V power supply, user selectable logic level [3.3 or 5V], Pn4 IO is accessible and PMC Bezel is mounted through the PCI Bezel. In Stock
1/2002 Developments: IP-Compact Flash
IP-CompactFLASH - CompactFLASH to IP Module bridge. Meets IP electrical and mechanical requirements. CompactFLASH connector on board. IO connector pinned out for IDE interface to allow a second CompactFLASH or other compatible hardware to be connected with a transition module. In stock.
11/2001 Developments: PCI LVDS 8T
PCI LVDS 8T : Dynamic Engineering successfully tests transmission between 8T and 8R designs. 64 Mb of data was transmitted across 8 channels simulataneously. The data was DMA transferred into the 8T, transmitted to the 8R and then DMA transferred from the 8R back into host memory. The received data was checked. The test was repeated in a loop with no errors. The test was run for 24 hours. Development work continues on the 8T driver and additional hardware testing. The second production order for 40 of the 8R boards was received.
10/2001 Developments: PCI LVDS 8R
PCI LVDS 8R : Dynamic Engineering completes the PCI LVDS 8R. The PCI LVDS 8R features 8 high speed LVDS channels which can receive and store data into 512 mB of on board SDRAM. The data can then be moved to host memory with scatter gather DMA. NT driver available. Custom digital data filtering available.
07/2001 Developments: PMC BiSerial Navy
PMC BiSerial Navy : Dynamic Engineering updates the PMC BiSerial to perform Manchester encoding and decoding for a USN program. Redundant transmit and receive channels
06/2001 Developments: PMC 4U
PMC 4U : Dynamic Engineering designs the PMC 4U to provide 4 UART channels plus Z85C30 Serial Communications Controller. Multiple IO standards supported including RS485, RS232, RS423, and RS188.
05/2001 Developments: PIM-Universal-IO
PIM-Universal-IO : Dynamic Engineering designs the PIM_Universal_IO to facilitate rear panel IO in cPCI based systems using PMC's. The PIM_Universal_IO provides the PMC front panel IO where rear panel IO is desired.
04/2001 Contract Award: PCI_LVDS_8T
PCI_LVDS_8T: Dynamic Engineering awarded 2nd design contract for a PCI card with 8 channels of LVDS output, digital filtering and storage. This board has up to 512 mb of SDRAM and scatter gather DMA capability.. ..
04/2001 Product Release: PMC PIM Module PIM modules now available for shipping
The PMC PIM's are 1/2 sized PMC cards mounted onto a PIM carrier board to allow for rear panel I/O. The PIM's can be used with any PMC card. This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891.
03/2001 News from Dynamic Engineering
* Navy contracts with Dynamic Engineering for Manchester design.
* IP-Crypto KYK-13 interface completed
03/2001 New Product Release - IP Parallel-BA1 "IP Tape"
Customer accepts protype - production units are in route to customer. The IndustryPack compatible IP-Parallel-IO board adds 48 channels of IO in one slot. Perfect for embedded control. All registers are read-writeable. Mezzanine boards. This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891.
View our other Industry Pack cards here: Industry Pack cards by Dynamic Engineering
02/2001 Dynamic Engineering Design Awards:
* Contract awarded to design PIM module for Teraburst.
* Contract awarded to design PMC-4U
02/01 New Product Release - S_A_Relay
Allows undetectable active monitoring and data altering of two ethernet (RJ-45) lines.
02/2001 New Product Release - IP BiSerial-RTN2
RTN2 is an update to the IP Biserial-BA2 with an expanded word counter, 16 Mb FIFO, programmable parity odd/even and on/off, programmable almost empty and programmable almost full interrupt capabilities added. IP, oscillator or user clock reference with 12 bit programmable divider for transmit frequencies. This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891. View our other IP Biserials cards here: IP BiSerial versions by Dynamic Engineering
11/00 New Product Release - IP Parallel IO
IndustryPack compatible IP-Parallel-IO board adds 48 channels of IO in one slot. Perfect for embedded control. All registers are read-writeable. Mezzanine boards, VME, PCI, and custom architectures are supported. I/O and embedded control are our specialties.
This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891.
11/00 - Dynamic Engineering Design Awards:
* Contract to design specialized Parallel I/O IP [IndustryPack] module.
* Network Physics awards contract to design ethernet relay bipass card and offset PCI extender
* Raytheon awards contract to design modifications to our IP BiSerial card.IP BiSerial
* Contract to design specialized BiSerial IP module with negative voltage output.
Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements
11/2009 Product Update Announcement PMC-BiSerial-III has a another
clientizedversion available the
NG8. The design features 2 channels with transmit or receive camera protocol. Each channel has Clock, HREF, VREF, BadPixel, and Pixel data [11-0]. "Channelized DMA"™ is used along with 133K x 32 FIFO to provide continuous operation. The transmit rate is selected with a PLL allowing for custom user frequencies. The image size is programmable. Blanking and active image areas are programmable. Interrupts, status and error checking. RS-485 is used for the IO.
10/2009 Product Update Announcement IP-Parallel-IO Windows® driver updated to include all models within the same driver package. Updated manuals available on the IP-Parallel-IO product page. The hardware is available in 7
flavorswith 48 TTL, 24 Differential IO, or 5 versions with mixed single ended and differential IO. The driver is available now and compatible with all Dynamic Engineering IP Carriers [PCI5IP, PCI3IP, cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP]. The driver is free when the IP is purchased with a Dynamic Engineering IP Carrier.
10/2009 New Product Announcement PCIeBiSerialDb37 design has been released. New member of industry leading BiSerial family. PCIe 1-4 lane version with 18 differential IO, DMA, Memory, programmable interrupts, terminations and plenty of room for complex state-machines. Initial implementation
LM9provides an interface for the ARC-210 radio. The PCIeBiSerialDb37 design is complete and ready for new client requirements. Windows® and Linux support.
6/2009 New Product Announcement PCI-ASCB design has been released. Implements 2 redundant channels of ASCB with standard pinout DB9 connectors mounted through PC rear bezel. Location for PMC or prPMC for local SW processing of ASCB data. Locations for optional FIFO´s. Windows® support.
5/2009 New Product Version Announcement PMC BiSerial III BA19 design has been released.
BA19is designed to interact using a
Master / Targetinterface based on a reference clock, byte wide LVDS data, and handshaking. The interface is used to stream data from an external source to the local disk using DMA and driver calls. The reference software has a complete application perfoming data capture to files using DMA and storing onto the local HDD. Windows® support.
4/2009 New Product Announcement ccPMC-HOTLink design has been released. Multiple HOTLink channels per conduction cooled PMC with RS-485 for a secondary low speed control bus. Each channel with independent DMA support. Programmable frequency operation. Transformer or direct coupled RX. LVDS or RS485 options for secondary bus. PECL on HOTLink channels. PLL support for HOTLink transmit control.
3/2009 New Product ccPMC-SpaceWire SpaceWire has been ported to the ccPMC platform. 4 independent channels per card each with DMA, Memory and Time Code support. Option for Radiation Hardened FLASH memory. Optional Larger FIFO´s. Windows® and Linux drivers plus reference application software available. Cables, SpaceWire specific debugging / breakout, cable to connector adapters and other interface support.
2/2009 New Product Enhancement: Customerized version ccPMC-Parallel-TTL design has been updated with a user specific version. The
BA18is based on the
BA17. The upper 32 bits have TimeStamp information with a 12K deep FIFO and DMA. Bits are programmable as to which cause the trigger to capture the time-stamp and the current data set. The design has been further enhanced with the addition of 8 A/D´s. The ADC outputs are filtered and the data stored when the programmable offset is exceeded. The HW automatically determines the current values, applies a programmed offset over and a separate programmed offset under the current value. When a new sample is detected outside of the range the sample is stored, time-tagged, and used as the new sample. The FPGA has been upgraded to a Spartan III 4000 in order to incorporate larger internal FIFO´s.
2/2009 New Product Enhancement: Customerized version ccPMC-Parallel-TTL design has been updated with a user specific version. The
BA18is based on the
BA17. The upper 32 bits have TimeStamp information with a 12K deep FIFO and DMA. Bits are programmable as to which cause the trigger to capture the time-stamp and the current data set. The design has been further enhanced with the addition of 8 A/D´s. The ADC outputs are filtered and the data stored when the programmable offset is exceeded. The HW automatically determines the current values, applies a programmed offset over and a separate programmed offset under the current value. When a new sample is detected outside of the range the sample is stored, time-tagged, and used as the new sample. The FPGA has been upgraded to a Spartan III 4000 in order to incorporate larger internal FIFO´s.
11/2008 New Product PC104p-SpaceWire SpaceWire has been ported to the PC104p and PCI-104 platforms. 4 independent channels per card each with DMA, Memory and Time Code support. Optional Larger FIFO´s. Windows® and Linux drivers plus reference application software available. Cables, SpaceWire specific debugging / breakout, cable to connector adapters and other interface support.
11/2008 New Product Enhancement: Customerized version The PMC-Parallel-TTL design has been updated with a user specific version. The
BA17has the standard features of 64 bitwise programmable TTL IO, and COS processing on the inputs. The upper 32 bits have TimeStamp information with a 12K deep FIFO and DMA. Bits are programmable as to which cause the trigger to capture the time-stamp and the current data set.
9/2008 New Product Enhancement: Customerized version The PMC-Parallel-TTL design has been updated with a user specific version. The
BA16has the standard features of 64 bitwise programmable TTL IO, and COS processing on the inputs. Two parallel, programmable DMA Ð FIFO based outputs and inputs have been added to support frequency controlled parallel IO. Linux driver support. Windows® on the way.
8/2008 New Product Enhancement: Linux Driver Utilize SpaceWire to communicate with the European Space Agency, and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a hierarchical point-to-point system with high speed paths. Dynamic Engineering supports SpaceWire with PMC, and PCI based hardware along with Windows® and Linux drivers. Cables and other hardware including the SpaceWire link tester
DESWBOare also available.
The SpaceWire driver includes
Baseand
ChannelLinux device drivers for the PMC-SpaceWire, and PCI-SpaceWire from Dynamic Engineering. Each design has four channels per board. A programmable PLL with four clock outputs is used to create separate programmable I/O clocks for each SpaceWire channel. Each channel has two data FIFOs, and two packet-length FIFO´s, for data transmission and reception. In addition external FIFO´s can be added to provide additional data storage.
When the Base module is installed, it interfaces with the PCI system configuration utility to acquire the memory and interrupt resources for each device installed. A SpaceWire
busis created for each channel with four allocated per card. The interrupt is assigned, and the address space partitioned for the four channel devices. When the Channel driver is installed, it probes the SpaceWire bus, finds, and initializes the four channel devices for each board. It allocates read and write list memory to hold the DMA page descriptors that are used by the hardware to perform scatter-gather DMA.
In this way each of the channels on the SpaceWire card can be treated separately for easy to write user level software. For example, large DMA transfers can be initiated without the software doing any arbitration between the channels as separate DMA engines are provided per RX and TX channel. The number of interrupts to handle can be drastically reduced with the channelized architecture.
The SpaceWire Linux driver comes with example test software that can perform DMA tests on the internal memory of the SpaceWire device or external loop-back testing between the ports. The driver handles the details including programming the PLL.
7/2008 New hires Dynamic Engineering has hired Nicola Leisses to work in the marketing and special projects group. Nicola is a recent graduate from the University of Santa Clara. Nicola graduated Magna Cum Laude with a BS degree from the Leavy School of Business.
6/2008 New and improved Product Enhancement: Updated, redesigned Linux base driver for PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP, and PC104p4IP carriers is done. The first child driver to go with the carrier drivers is for IP-QuadUART, and is now completed. The carrier driver comes with a
genericdriver module to act as the child driver for IP´s without a Linux driver written. The generic driver allows third party designs without native linux drivers to be used with the Dynamic Engineering Carrier Drivers for Linux as well as any Dynamic Engineering cards not yet supported. Example software using the generic driver is included.
6/2008 New Product Announcements: PCIeBPMCX1 and PCIeBPMC
The PMC carrier family has been updated to include two new PCI Express based single PMC carriers using the TSI384. The PMC side of the bridge is programmable bus speed and width. The X1 version supports true PCI-X speed at the PMC with 4 lane PCIe operation. The PCIeBPMC uses only 1 lane to provide 32/33 capability to the numerous single slot options in new PC´s. Pn4 is routed to a SCSI connector with matched length differential routing and 100 ohm impedance. The design features an efficient built-in power supply, options for "Zero Slot Fans"™, Lane and Power status LED´s. Both versions are immediately available from stock.
5/2008 New and improved Product Enhancement: Updated, redesigned Linux base driver for PCI3IP, PCI5IP carriers is done. Now porting to cPCI2IP, cPCI4IP, PC104pIP, PC104p4IP. First IP level driver is for the IP-QuadUART. Generic driver included with carrier driver allows any IP to be used with the carrier.
4/2008 New Product Enhancement: cPCI Receiver Controller
The cPCI Receiver Controller is a 3U 4HP design that can be used for many purposes. The primary design implementation is to act as the controller slice within a digital receiver. The host computer can access the Receiver Controller over the PCI bus within the cPCI system. The Receiver Controller buffers commands from the host and converts them to the appropriate format to interface with the rest of the Digital Receiver. The initial design is controlled with several SPI [Serial Peripheral Interface] buses. In addition A/D, D/A, Temperature sensor, UART, Clock references are supported.
Available now.
3/2008 New Product Enhancement: IP-CAN
Talk to your car or other CAN device, snoop a bus or be an active participant. IP-CAN is a versitile design that has been updated for better logistical support. IP-CAN has been adapted to add software selectable termination options. Using calls from the new IP-CAN driver for Windows® the user can configure the termination to match end-of-bus or mid-bus topologies without physically changing the hardware. The driver supports IP-CAN on all Dynamic Engineering IP carriers. The driver and hardware have been tested at high and low frequencies over long and short cables with multiple nodes. The driver supports the Pelican and standard modes of operation. Multiple IP-CAN boards can be used in the same system.
Available now.
1/2008 New Product Announcement: PCI-Harpoon
PCI-Harpoon can be used for simulation, control, command and other embedded IO functions. The
Harpoonis being used for similation in its first applicaion. The client is using the Harpoon to simulate part of their system to allow testing of the rest of their system. The design has 4 channels to allow testing of multiple target hardware sets in parallel. Each channel has opto-isolated inputs set-up for 28V, High Side switches utilizing opto-coupled FETs with 60V 1.5A max per switch, Low Side switches also with opto-coupled FETs, 115V detection, and differential IO. The differential IO is configured to command and respond to the system under test. PCI-Harpoon has a large FPGA to allow for customerized versions in new applications. Window®s driver and application software available. Cables and breakout [terminal strip] adapters also available.
Available now.
10/2007 Product Update Announcement: cPCI4IP
The cPCI based IndustryPack® Carrier with 4 slots has been updated to provide a
mini-mapversion with a smaller PCI memory requirement per card. The
-MMversion requires one eighth of the PCI memory assets of the standard memory map. The MEMory Space is still supported for each of the IP modules installed. 64K is provided per slot instead of the full MEMory Space. For designs not using the IP MEM Space or only using a fraction of it the -MM option reduces the PCI memory space requirement allowing more cards to be installed on the bus.
Available now.
10/2007 Product Update Announcement: PMC-SpaceWire and PCI-SpaceWire
The Industry standard PMC and PCI SpaceWire designs have been updated to include an option for deep FIFOs on channel 0. 512K organized as 128K x 32 is available to support TX and RX on channel 0. Add
-128to part number to select the deep FIFO option.
Available now.
9/2007 New Product Announcement: PMC-BiSerial-III-TRANS
The Industry leading PMC BiSerial III is now available in a Conduction Cooled, Transformer Coupled configuration. The IO are transformer coupled RS-485 and support up to 40 MHz. The IO is matched length differentially routed to Pn4. Extended temperature operation is standard. Conformal coating is an option. The first customer design is complete with the
HW4version - 8 channels of manchester encoded IO with half and full duplex operation.
Available now.
9/2007 New Product Announcement: PMC-Parallel-TTL
Most systems need TTL lines and in some cases a lot of them. The PMC Parallel TTL packs 64 TTL IO with Change Of State
COSprocessing, programmable interrupts, integrated PCI interface with DMA capability, multiple clocking options and room to add new features within the FPGA into a PMC module. For systems requiring more than 64 lines the DIP Switch can be used to facilitate multiple cards with unique settings. Options include: front, rear or dual IO , extended temperature, conformal coating, 3V or 5V IO, and transorb protection. The PMC Parallel TTL is an upgrade for the PMC Parallel IO design. It is recommended for new system implementations. Press Release
Available now.
8/2007 New Product Announcement: Dynamic Engineering rugged chassis PCI-104, PC/104p and PC104 applications
Rugged chassis with built in heat sink, mounting flange, gaskets, and an internal shock mounted card cage. Chassis is available in multiple lengths.
Press Release
6/2007 New Product Announcement: Dynamic Engineering Power Supply for PCI-104, PC/104p and PC104 applications
Create +5V, +3.3V, -12V and -5V from a 12V input - wall mount transformer, battery or similar. 8A on the +5 and +3.3V rails, 4A on the -12 and -5V rails max. +12V routed through and fused at 4A to stack. High efficiency switcher designs with fused filtered power output. Delayed turn-on to minimized inrush current. Works with any PCI-104, PC104, or PC104p stack.
5/2007 New Product Announcement: PMC-BiSerial-III-LM6
Two serial protocols with test ports plus direct and DMA support. Customerized version of PMC-BiSerial-III design with VHDL and Windows® driver modified for this effort. Dynamic Engineering features custom upgrades to the
BiSerialand other standard designs. What can we design for you?
3/2007 We moved: Dynamic Engineering has relocated to a new larger facility located at 150 Dubois Street, Suite #3, Santa Cruz, Ca. 95060. The new facility features advanced manufacturing capabilites to allow both standard and ROHS processing to occur, on-site support for our clients, more storage for shorter lead times, and creative space to help expand our Dynamic Designs
2/2007 New Product Announcement: Dynamic Engineering IP-1553 1 and 2 channel Dual Redundant Mil-STD-1553
By customer request Dynamic Engineering has developed a 1553 interface on an IndustryPack® format card. The ACE industry standard interface is compatible with the current and previous versions of 1553. Speeds up to 1 MHz. Multiple programmable interface modes. Direct or transformer coupled interface is shunt programmable.
1/2007 New Product Announcement: PCIBPMCX1
The PMC carrier family has been updated to include a single PMC carrier using the Intel 31154 PCI/PCI-X bridge. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The Pn4 connector is routed to a SCSI connector with matched length differential routing and 100 ohm impedance.
1/2007 IP Crypto: Dynamic Engineering IP-Crypto
By customer request Dynamic Engineering has conformal coated and temperature tested 10 units. The IP-Crypto units were installed onto multiple PCI3IP carriers and loaded into a temperature chamber. The units were cycled from -30C to +80C with 2 hour dwell times at each extreme for 6 cycles powered off. The IP-Crypto´s were then tested - running the Dynamic Engineering carrier driver with IP-Crypto driver module over a range of 0C to 50C with 2 hour dwells for 4 cycles. All units passed all tests first time through.
11/2006 New Product Announcement: Dynamic Engineering IP-CAN Dual Channel Controller Area Network card
By customer request Dynamic Engineering has developed a dual CAN interface on an IndustryPack® format card. The SJA1000 / SJA1041 industry standard interface is compatible with the current and previous versions of CAN. Speeds up to 1 MHz. Multiple programmable interface modes. Direct or isolated interface.
10/2006 New Product Announcement: Dynamic Engineering Extended Temperature 6U cPCI Dual PMC Carrier
By customer request Dynamic Engineering has developed a dual PMC extended temperature version of the popular cPCIBPMC design. The design effort included switching to a new bridge to meet the temperature and timing requirements. The new bridge brings new features including the ability to operate the PMC side at a higher clock rate than the cPCI side. The new bridge also has built in features for local address spaces, using the PMC in monarch mode, and operating in transparent or non-transparent modes. The design is ready for your cPCI PMC applications. Please contact Dynamic Engineering with your custom requirements.
8/2006 New Product Announcement: Dynamic Engineering Extended Temperature 3U cPCI PMC Carrier
By customer request Dynamic Engineering has developed an extended temperature version of the popular cPCIBPMC design. The design effort included switching to a new bridge to meet the temperature and timing requirements. The new bridge brings new features including the ability to operate the PMC side at a higher clock rate than the cPCI side. The new bridge also has built in features for local address spaces, using the PMC in monarch mode for the secondary side, and operating in transparent or non-transparent modes. The design is ready for all of your PMC applications. Please contact Dynamic Engineering with your custom requirements.
8/2006 New Product Announcement: Dynamic Engineering SpaceWire Connector Board "DESWCB"
The DESWCB is used to interface custom cables to SpaceWire cables. Up to 28 SpaceWire connectors / cables can adapted to your custom cable per DESWCB. Please contact Dynamic Engineering with your custom requirements.
8/2006 New Version Announcement: IP-BiSerial-BA13
The IP-BiSerial-BA13 has been released. The new version of the IP-BiSerial-IO is available with programmable 16 or 32 bit serial data, programmable parity. programmable Transmit clock rate. Wide range of receive rates, 2K of FIFO per channel. One transmitter and one receiver per board. Please contact Dynamic Engineering with your custom requirements.
7/2006 New Product Announcement: PC104p-BiSerial-III-TG1
The PC104p-Biserial-III-TG1 has been released. The buoy based hardware will read sensors located within the buoy to allow the data to be recorded and processed. Four independent DMA based receive channels per card. 3 wire interface using RS-485 compatible hardware. An additional transmit channel is supplied for loop-back. Please contact Dynamic Engineering with your custom requirements.
7/2006 New Product Announcement: PC104p-BiSerial-III-BA14
The PC104p-Biserial-III-BA14 has been released. The BA14 interface has UART like features with a serial rate of 6.25 MHz, start, stop, marking states, and 16 bit data preceded by a Command / Data indicator. The transmit and receive channels are independent and supported by DMA. Please contact Dynamic Engineering for your custom version.
7/2006 New Product Announcement: PMC-Wizard
The PMC-Wizard is intended for use in ultra high-speed bidirectional point-to-point data transmission systems. The primary application is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 Ω. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media, and the noise coupling to the environment. The PMC-Wizard can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit / receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, twisted pair, or an optical link. Data is then reconstructed into its original parallel format. Significant power and cost savings are realized when compared with parallel solutions. PMC-Wizard is provided with independent DMA support for each input and output channel. Windows® driver available.
6/2006 New Product Announcement: PC104p-BiSerial-III
The PC104p family has been updated with a new member of the BiSerial family. The updated BiSerial-III features a Spartan III 1500 FPGA, 16 transceivers (RS485 or LVDS), 8 bit TTL port, (4) DAC, (4)ADC, PLL. The PCI interface has been updated to work with DMA. Each IO channel can have a separate DMA channel to allow multiple data streams to be handled with very low overhead from the CPU. The first application will be installed in a buoy. What do you need? Please contact Dynamic Engineering for your custom version.
3/2006 New Product Announcement: PMC-XM
The PMC family has been updated to include a user programmable Virtex based mezzanine capable PMC design. The PMC-XM has a "fixed" FPGA which handles the PCI bus including a 4 channel DMA function and a user programmable Virtex SX35 device. The Virtex is supported with a PLL, RAM, and a mezzanine position. The design is in final integration.
2/2006 New Product Announcement: PMC-MC-X2
The PMC carrier family has been updated to include a Dual PMC carrier. The PMCs are installed on both front and rear surfaces for a dense packaging solution. 64/66 and 32/33 operation is supported. It is anticipated that a PrPMC is installed into slot 0. On board clock distribution, interrupt routing, and bus arbitration. A single 12V power supply [wall transformer] is used along with the internal power supplies to power the +5, +3, and +/ 12V rails. VIO is programmable. "1/2 size version of X4"
1/2006 New Product Announcement: PMC-MC-X4
The PMC carrier family has been updated to include a Quad PMC carrier. The PMCs are installed on both front and rear surfaces for a dense packaging solution. 64/66 and 32/33 operation is supported. It is anticipated that a PrPMC is installed into slot 0. On board clock distribution, interrupt routing, and bus arbitration. A single 12V power supply [wall transformer] is used along with the internal power supplies to power the +5, +3, and +/ 12V rails. VIO is programmable.
12/2005 New Product Announcement: cPCIBPMC3U64-ET
The PMC carrier family has been updated to include an Extended Temperature version of the popular cPCIBPMC 3U carrier. The extended temperature version will support -40 to +85 C operation with 64/66 or 32/33
11/2005 New Product Announcement: PCI SpaceWire
Dynamic Engineering has won a contract to port the popular PMC SpaceWire design onto the PCI format. The PCI SpaceWire will have 4 channels supported through the PCI Bezel on standard micro D connectors. The PCI SpaceWire will be completely compatible with the PMC-SpaceWire, and eliminate the need for a carrier in PCI systems. It is anticipated that the design will be available for delivery in early May 2006.
10/2005 New Product Announcement: PCIBPMCx2
The PMC carrier family has been updated to include a dual PMC carrier using the Intel 31154 PCI/PCI-X bridge. One PCI slot provides two PMC positions. The PMC side of the bridge is programmable for VIO, interrupts, bus speed and width. The primary and secondary sides can operate at different bus speeds and data widths. The seconday side can be hidden from the primary side to support PrPMC applications. For example: use the main PCI bus to load software into the PrPMC, then use the hidden mode to communicate between the PrPMC, and a second IO based PMC. Ideal for embedded applications with high speed local processing without depency on the main PCI bus timing.
9/2005 Product Update: IP-OptoISO-16
The IP-OptoISO-16 is an IndustryPack Module with 16 optically controlled FETs. Each FET acts as a single pole normally open photovoltaic relay. The solid state approach has several advantages including bounce free operation, low on resistance, long life, fast switching, and higher reliability when compared to relays. The IP-OptoISO-16 has been enhanced with the D and S side now available at the IO connector to allow high and low side switching. Each switch is independent for mixed mode operation. As of 9/12/05 all new orders will receive revision C . The new design is compatible with the previous revisions.
The FETs switch the Drain and Source. The Drain or Source for each switch is tied to a reference voltage. When the switches are closed the S
8/2005 New Product Announcement: PMC-BiSerial-III
The PMC BiSerial family has been updated to include a Spartan III [Xilinx] based card with expanded capabilities.. Building on the knowledge and experience gathered from multiple IP and PMC BiSerial implementations and adding in the latest technology has created the PMC-BiSerial-III. The BiSerial III features completely isolated FIFOs with 32 bit ports for increased adaptability and performance. The [34] RS-485 / LVDS buffers have programmable termination, and direction control. Half-Duplex, Full-Duplex and single ended systems can be configured with software and VHDL. The denser, faster FPGA will implement the most complex state-machines. The prototype fabs are in test for the initial customer specific version; 32 Manchester channels with independent memories in one PMC.
7/2005 New Product Update: PMC-SpaceWire
Dynamic Engineering has delivered the first version of PMC-SpaceWire to three customers. The initial fab lot has been depleted. The design is being updated for ROHS and incorporation of design updates. The updated revision will be available late August / early September 2005. PMC-SpaceWire implements SpaceWire in a convenient PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS signaling and a 9 pin MDM connector. PMC-SpaceWire provides 4 SpaceWire attachments allowing your host to directly communicate with multiple devices. The hardware is supported with a Windows® driver. PMC-SpaceWire has been tested at 200 MHz. Test cables have been developed to meet the base requirements of SpaceWire - a good combination of capabilities and lower cost.
6/2005 Product Update Announcement: ROHS compliance
Dynamic Engineering has a plan in place to meet the ROHS requirements by the 2006 implementation deadline. Dynamic Engineering has decided to go with Gold instead of Tin for superior performance in the short and long term life of our product. Many of the components that we use already meet the ROHS requirements. When the rest of the components become available we will switch our process over to use ROHS compliant solder paste etc.
5/2005 New Product Announcement: PC/104p-BaseBoard
The BaseBoard is part of the PC/104 Module family of modular I/O components by Dynamic Engineering. The BaseBoard is used to integrate a PC/104p stack with the power supply, 35 Optocoupled Inputs, 37 Optocoupled Outputs, 2 UART - RS-485 ports, 2 ARINC 429 - TX/RX, 4 ADC Ports, and 4 DAC Ports comprize the onboard feature set of the BaseBoard design. The Right hand PC/104 slot is designed to be occupied by the Power Supply module which accepts 28V and supplies the standard PC/104 voltages on the ISA connector. The left hand slot is used to add a PC/104p stack.
4/2005 New Version Announcement: PMC-Serial-M1
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provide four RS-422 UART channels and no SCC
The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating frequencies. Dynamic Engineering performed the design to support Mitre. The hardware is supported with an engineering kit.
4/2005 New Product Update: PMC-SpaceWire
Dynamic Engineering is under contract to make the first customerized version of PMC-SpaceWire. PMC-SpaceWire implements SpaceWire in a convenient PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS signaling and a 9 pin MDM connector. PMC-SpaceWire provides 4 SpaceWire attachments allowing your host to directly communicate with multiple devices. The hardware is supported with a Windows®; driver. PMC-SpaceWire has been tested at 200 MHz. PMC-SpaceWire is in final integration with customer equipment with first deliveries expected in the start of May/2005. Test cables have been developed to meet the base requirements of SpaceWire - a good combination of capabilities and lower cost.
3/2005 New Product Announcement: BaseBoard
Dynamic Engineering is under contract with BAE to develop a specialized PC/104p ³BaseBoard². The BaseBoard will have two PC/104 positions allowing a power supply module to be installed in one and a PC/104p stack to be installed in the other. The BaseBoard acts as stack position 0 utilizing a Xilinx FPGA to interface with the PCI bus. BaseBoard has Optocoupled IO, UARTs, ARINC 429 ports, DAC and ADC ports. This is a quick turn project with delivery expected the first week of May 2005.
2/2005 New Product Announcement: cPCIBPMC3U64
Dynamic Engineering has completed the cPCIBPMC3U64 design. The Compact PCI carrier provides 1 PMC position on a 3U 4HP cPCI card. The configuration is intended for 64 bit cPCI backplanes. The bridge provides isolation from the backplane allowing for 3.3 or 5V PMCs to be installed and to make adjustments in clock speeds. VIO is jumper selectable on the PMC side of the Bridge. There are options for connecting the Ethernet, Serial and I2C ports. IO is through the cPCI bezel.
Another version is coming soon which will have a 32 bit PCI bus and user IO to the rear panel.
1/2005 New Version Announcement: PMC-Serial-RTN5
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provide an option for RS-232 operation with the Serial Communications Controller, plsu 2 RS-232 and 2- RS422 channels on the UART.
The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating frequencies. Dynamic Engineering performed the design to support Raytheon and the US Coast Guard. The hardware is supported with an engineering kit. A Windows driver is being written for the PMC-Serial-RTN5
12/2004 Updated Product Announcement: PCI-NECL-ASN1
The PCI-NECL-ASN1 supplies 20 ECL transmitters and 20 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. The 20 inputs and outputs can be programmed to make parallel and serial interfaces. The spare IO can be used as a parallel port. PCI-NECL-ASN1 is a customerized version of the PCI-ECL card. Dynamic Engineering performed the design to a parallel interface. The hardware is supported with a Windows¨ driver. The driver and design are available as part of the engineering kit to allow customers to create their own custom interfaces. The on-board FLASH is reprogrammable to support custom requirements.
11/2004 Driver available: PMC Parallel IO
The PMC Parallel IO is now supported by a Windows® 2000/XP Compatible driver. The driver will decrease your time to market with direct access to the PMC Parallel IO hardware using standard C/C++ calls.
The PMC Parallel IO provides the common requirement of single ended IO for embedded systems. Each of the 64 IO are independently programmable for input and output. Front and rear panel IO are available. Interrupts are supported. Custom IO requirements are supported with a reprogrammable FPGA device.
10/2004 updated Design: PCI_Altera_485/LVDS
The PCI-Altera-485/LVDS has been updated to have the option to use a FLASH based PROM to load the Altera at power-up or to load from the Xilinx via software and the PCI bus. For applications requiring a quick start the PROM can configure the Altera before the OS is running. The PCI-Altera provides reconfigurable logic with a 20K400E plus DMA, 16 FIFOs, 8 triple PLLs, 12 TTL IO, and 40 RS-485 or LVDS IO.
10/2004 New Version Announcement: IP-HaveQuick is a new version of the IP-Parallel-HV
The HaveQuick version provides master and target capability to interface with TOD [time of day] equipment using the HaveQuick manchester encoded interface standard. As a target the time code from the TOD unit can be read by the host for an accurate time. The seconds, minutes, hours, days and years are encoded into the format. The IP-HaveQuick locally interpolates to provide a higher resolution time synchronized to the 1PPS [one pulse per second] reference and time code data. As a Master the hardware can be programmed with the start time and then run independently to provide a reference. The hardware is supported with an IP driver compatible with the Windows 2000® and XP® OS.
10/2004 New Version Announcement: PMC-BiSerial II-PS2 is a new version of the PMC-BiSerial II
The PS2 version provides eight serial channels and an 8 bit parallel port with RS-422/485 IO. The serial channels are configured with 4 transmit and 4 receive. The protocol provides a Data, Clock and Strobe interface. The transmit rate is programmable up to 20 MHz. Each channel [8] has a 128 x 32 FIFO for data storage. Lower cost version of the standard PMC-BiSerial product with smaller Block RAM FIFOs and more channels.
9/2004 New Product Announcement: cPCI4IP
The cPCI4IP provides four IndustryPack® slots in one 6U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in each slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. Windows® driver available.
9/2004 Updated Product Announcement: cPCI2IP
The cPCI2IP provides two IndustryPack® slots in one 3U 4HP cPCI board. Use your favorite IP modules in a Compact PCI environment. The updated design supports 8,16,and 32 bit data transfers to 16 and 32 bit single and double wide IPs. IO, ID, Interrupt and Memory spaces supported. 8 and 32 Mhz operation in either slot. Fused filtered power to each slot. IO options for rear panel, front panel and both. Watchdog timer with bus error information per slot. Windows® driver available.
9/2004 New Version Announcement: PMC-Serial-RTN4
Synchronous and Asynchronous programmable IO is provided by the PMC-Serial design. UART, HDLC, BiSync etc. are supported.
The PMC-Serial has been updated provde an option for RS-232 operation with the Serial Communications Controller.
The L3 version is available with RS-485 IO on the SCC.
Both models have RS-232 IO for the QuadUART. The FPGA supports the UARTs with write-through and pre-read capabilities plus data width control for improved performance. The UARTs have 128 position FIFOs for each channel. Multiple on-board references are available to provide a multitude of operating frequencies. Dynamic Engineering performed the design to support Raytheon and the US Coast Guard. The hardware is supported with an engineering kit.
8/2004 New Product Announcement: PCI-NECL-ASN1
The PCI-NECL-ASN1 supplies 20 ECL transmitters and 20 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. PCI-NECL-ASN1 is a customerized version of the PCI-ECL card. The Interface has 16 bit parallel data with reference clock, data valid, data ready, and buffer limit handshaking. Dynamic Engineering performed the design to support Asine Ltd. The hardware is supported with a Windows¨ driver.
8/2004 New Product Announcement: PCI-NECL-XG1
The PCI-NECL-XG1 supplies 19 ECL transmitters and 19 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. The 19 inputs and outputs can be programmed to make parallel and serial interfaces. The spare IO can be used as a parallel port. PCI-NECL-XG1 is a customerized version of the PCI-ECL card. Dynamic Engineering performed the design to support XG Technologies for a digital receiver interface which operates at 170.6 MHz.. The interface is a 3 wire serial implementation leaving 2 - 16 bit parallel ports. The hardware is supported with a Windows¨ driver.
7/2004 New Product Announcement: PMC-SpaceWire
Dynamic Engineering is under contract to make the first customerized version of PMC-SpaceWire. PMC-SpaceWire implements SpaceWire in a convenient PMC format. Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-50-12A specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths. The SpaceWire specification calls for LVDS signaling and a 9 pin MDM connector. PMC-SpaceWire provides 3 SpaceWire attachements allowing your host to directly communicate with multiple devices. The hardware is supported with a Windows¨ driver.
6/2004 New Product Announcement: PCI-Serial_ECL
The PCI-Serial-ECL supplies 19 ECL transmitters and 19 ECL receivers plus 12 TTL IO. The IO are supported with DMA and state-machine control plus a storage FIFO for data buffering. Custom frequencies can be programmed into the PLL. The 19 inputs and outputs can be programmed to make parallel and serial interfaces. The spare IO can be used as a parallel port. Dynamic Engineering is under contract to make the first customerized version of the PCI-Serial-ECL for a digital receiver interface which operates at 170 MHz.. The interface is a 3 wire serial implementation leaving 2 - 16 bit parallel ports. The hardware is supported with a Windows¨ driver.
6/2004 New Product Announcement: PC/104p-BiSerial
The BiSerial family has been expanded to include a PC/104p version of the design. The new implementation builds on the PMC-BiSerial-II and IP-BiSerial adding ADC and DAC capabilities. High speed programmable FPGA for application specific state-machine implementations. 16 RS-485 transceivers which can be swapped with LVDS IO, 4 ADC [16 bit, 200 KHz.] , 16 DAC [16 bit, 200 KHz] and 8 TTL make up the IO. Use for memory buffered communications and control, hardware interface simulation, command and control etc. BiSerial designs have been used for industrial control, test support, simulation of other equipment, "glue" between incompatible systems, communications, and more. Dynamic Engineering is under contract to make the first customerized version of the PC/104p-BiSerial for a LASER interface. The hardware is supported with a Windows¨ driver.
5/2004 Product Update Announcement: PCI5IP-XP/2000
PCI5IP-XP/2000 is now available to support the Windows¨2000 OS. The PCI5IP-XP/2000 driver is a "Parent" Driver for Windows¨XP or Windows¨2000 systems. The driver facilitates the integration of up to 5 IP modules per PCI5IP and up to 10 PCI5IPs per system providing the kind of flexibility that system designers need in todays fast changing high tech market place. The driver is a purchase once and use many item - no additional royalties etc. for same company use. The Driver and PCI5IP are stocked items.
3/2004 Product Update Announcement: PCI-Altera-485/LVDS
The PCI-Altera-485 has been updated to have a build option to install LVDS transceivers creating the PCI-Altera-LVDS. There are 40 transceivers on the card and the transceivers can be implemented with 485, LVDS or mixed. The 485 transceivers are rated for 40 MHz operation. The LVDS transceivers are rated for 200 MHz operation. In addition the PCI-Altera Windows¨ driver has been updated to support XP and 2000. The PCI-Altera is designed to accept user VHDL files and the generic driver allows the user to communicate with their custom implementation using standard C. Easy to install, easy to load, easy to use.
2/2004 New Product Announcement: PCI Cable adapter to support IP-Crypto and IP-Tape
The Cable Assembly Crypto/Tape interconnects the IP Module Carrier and the PCI Bezel via a connector board and and internal ribbon cables. The IP-Crypto is broken out to an RJ45 and the IP-Tape to a SCSI connector. The IP-Tape connector has additional pins for"self-healing" fused power and ground.
2/2004 New Product Announcement: Single Slot IP Module carrier for PC/104p applications
The PC104pIP lets you mount a an industrypack¨ module onto a PC/104p in a standard PC/104p slot. The PC104pIP is based on the PC104p4IP design and features 8/32 MHz IP clock selection, fused filtered power, watchdog timer, 32 bit data handling, little/big endian support and more.
1/2004 New Design: PCI <-> PC/104p adapter
The PCI2PC104p lets you mount a PC/104p devide in a standard PCI slot. The PCI2PC104p has two configurations to support production and test. Testpoints are provided for the PCI signals in the test configuration.
1/2004 New Design: Cable adapter
The IP-Crypto and IP-Tape are now supported with a cable adapter. The cable adapter converts from ribbon cable [2 x 50] to RJ-435 and SCSI III connectors. The RJ-45 has the IP-Crypto interface and the SCSI III connector has 1:1 from the ribbon plus additional fused power and ground. The SCSI connector can be used to support any IP.
1/2004 New Design: Windows¨XP and 2000 drivers for the IP Crypto.
The IP-Crypto drivers are "Child" Drivers used with a "Parent" driver for the carrier the IP-Crypto is mounted to. For example with the PCI3IP the IP-Crypto can be installed into a standard PCI slot and controlled with standard C software and Windows¨2000 or XP operating systems. The IP-Crypto driver comes with source, example calling program and documentation.
12/2003 New Design: PCI_Altera_485_XP
The PCI-Altera-485-XP driver is a "Parent" Driver for Windows¨XP systems. The driver facilitates the operation of the PCI-Altera-485. Multiple PCI-Altera-485's are supported per system providing the kind of flexibility that system designers need in todays fast changing high tech market place. The PCI-Altera-485 driver comes complete. The base driver provides functionality to load the Altera with the user design, recognize different Altera implementations and load the appropriate child driver, and manage the PCI side of the design . The reference design [VHDL and load file] provided with the driver supports the basic features on the PCI-Altera-485 - PLLs, FIFOs etc.
11/2003 New Design: PMC-Serial
The PMC-Serial is an upgrade and replacement for the PMC-4U. The PMC-Serial features up to 8 UART channels, an SCC, RS485, RS232, RS188, RS423 options for IO. The standard configuration has 4 UART channels and 2 SCC channels. The UART is supported with 128 Deep FIFO per channel and performance logic for effecient operation on the PCI bus.
11/2003 New Design: IP-BiSerial-Miller
The IP-BiSerial-MLR is what you need to connect your system to a "Miller" encoded source and to transmit to another "Miller" encoded device. The design features 16K bytes FIFOs, programmable interface rates, programmable sync pattern, programmable frame length, programmable interrupts and more. Miller encoding provides a 50% duty cycle [overall] data with embedded clock interface. The encoding technique utilizes the time between transitions to define the data. Ideal for telemetry and fiber applications. A Windows¨XP driver is available.
10/2003 New Design: PCI3IP-XP
The PCI3IP-XP driver is a "Parent" Driver for Windows¨XP systems. The driver facilitates the integration of up to 3 IP modules per PCI3IP and up to 10 PCI3IPs per system providing the kind of flexibility that system designers need in todays fast changing high tech market place. The PCI3IP-XP driver comes complete with a generic IP driver to allow the use of IndustryPack¨ Modules that do not have an IP driver designed.
10/2003 Updated Design: PMC2PCI
The PMC2PCI by Dynamic Engineering integrates A PCI slot into a PMC environment. Use your favorite PCI card with a PMC carrier. 32/33 and 64/66 operation. 3.3 or 5V IO. Now with a more efficient switching 3.3V power supply design. User shunt to select PMC 3.3 or regulated 3.3. Please look at the data page for a complete description.
9/2003 New Design: PC104p4IP
The PC104p4IP by Dynamic Engineering integrates your favorite IndustryPacks with the PC/104+ module system. 4 IPs can be mounted to a single PC/104 slice. Fused filtered power on each slot, 8/16/32 bit operation with 16 and 32 bit IP modules, independent 8/32 MHz selection and more. Please look at the data page for a complete description.
5/2003 New Design: IP-Pulse
The IP-Pulse by Dynamic Engineering solves your programmable pulse generation requirements with 4 channels in a single IP Module. Each channel is independent and can be programmed with the pulse width and time between pulses. nS to seconds. The output pulses can be sent continuously or for a pre-programmed count. The four channels can be synchronized or started independently. Interrupt or polled operation.
5/2003 Updated Design: PCI3IP
PCI3IP-XP and Linux drivers coming soon! The PCI3IP by Dynamic Engineering has been updated with an alternate user interface. The PCI3IP initializes into the unifed (legacy) register set to support current installations. The distributed register set is selected with a control bit in the base register. The additional features will allow drivers written for the PCI5IP to be ported to the PCI3IP and vice-versa.
5/2003 New Design: PCI5IP-XP
The PCI5IP-XP driver is a "Parent" Driver for Windows¨XP systems. The driver facilitates the integration of up to 5 IP modules per PCI5IP and up to 10 PCI5IPs per system providing the kind of flexibility that system designers need in todays fast changing high tech market place.
5/2003 New Design: IP-BiSerial-NG4
Software programmable 3/4 wire modes, parity, transmit frequency, the width of the synchronization pulse, the time delay after the sync and the start of data, and the time between data words. The word transfer has an associated Word Sync signal to provide for framing and error checking. The Frame sync signal provides for message level synchronization. The Ng4 has programmable receive word count and receive all mode. The IP BiSerial NG4 has a 50 MHz reference oscillator.
4/2003 New Design: cPCI2PMC
The cPCI2PMC ( cPCI to PMC ) cPCI2PMC adapter / carrier converter card provides the ability to install a PMC card into a standard cPCI slot. The cPCI2PMC has a PMC card slot mounted to a universal 3U 4HP cPCI card. Suitable for 32/64 with 33/ 66 MHz bus operation. The PMC user IO connector Pn4 is optionally connected to J2 for rear panel IO. The PMC bezel connector is mounted though the cPCI mounting bracket.
4/2003 New Design: cPCI2IP
The cPCI [CompactPCI] compatible cPCI2IP cPCI2IP design adds 2 Industrypack compatible slots to your cPCI host. The cPCI2IP acts as an adapter, converter, carrier, or bridge between the cPCI bus and your IndustryPack hardware. The cPCI2IP is a 3U 4HP cPCI design with 2 IP slots.
3/2003 New version: IP-BiSerial-Q1
New version of the IP-BiSerial-IO designated IP-BiSerial-Q1 completed for QinetiQ The IP-BiSerial-Q1 features 16 or 32 bit programmable data length plus parity, bursted clock with frequency options and RS422 [RS485] IO.
3/2003 Updated Design: PCI3IP
The PCI3IP is now updated to be PCI 2.2 compliant and PCI universal voltage. The updated version is a drop in replacement for the previous PCI3IP revision. The PCI3IP features FAST¨ technology for high performance accessing your IndustryPack¨ modules.
2/2003 New Design: IP-OptoISO-16
16 Optically Isolated 0-60V 1.5A outputs - IndustryPack Product now available for ordering. Please e-mail sales@dyneng.com
1/2003 Design Award: IP-OptoISO-16
16 Optically Isolated 0-60V 1.5A outputs - IndustryPack Module design awarded to Dynamic Engineering. Product available for shipping March 1, 2003. Please e-mail sales@dyneng.com
1/2003 Developments: IP-OctalSerial
8 Channel Serial Data Interface IP Module shipped to customer. Please e-mail sales@dyneng.com
1/2003 Developments: IP-QuadUart-485
Customized version of the IP Quad UART ships to customer. Please e-mail sales@dyneng.com
8/2002 Contract Award: PMC-0C12
L3 Communications has awarded an new development contract to Dynamic Engineering to create the PMC-OC12. The PMC-OC12 development will be a quick reaction program to provide an OC12 capable fiber interface on a PMC format card. The Agere "Ultramapper" will be utilized to provide the protocol processing.
8/2002 -NG2 ships: IP-BiSerial-NG2
The IP-BiSerial update to create the IP-BiSerial-NG2 has been completed and the hardware shipped.
7/2002 -S311 ships: PMC-BiSerial
The PMC-BiSerial-S311 Shipped to the customer and is now in integration at their facility. The PMC-BiSerial-S311 was delivered with an NT driver and PCI adapter to allow Northrop Grumman to interface to legacy radar systems from a standard PC.
7/2002 Contract Award: PMC-BiSerial
BAE Systems has awarded an upgrade contract to Dynamic Engineering to create the PMC-BiSerial-BAE1. The PMC-BiSerial-BAE1 will feature a synchronous serial differential interface to a combination time distribution network and control data. Independent transmit and receive channels.
7/2002 Contract Award: IP-BiSerial
Northrop Grumman Corp. has awarded an upgrade contract to Dynamic Engineering to create the IP-BiSerial-NG2. The IP-BiSerial-NG2 will feature a standard satelite interface [Frame Sync, Word Sync, Data and clock]. Independent transmit and receive channels. Programmable parity, length, and data rates.
6/2002 Contract Award: PMC-BiSerial
Northrop Grumman Corp. has awarded an upgrade contract to Dynamic Engineering to create the PMC-BiSerial-S311. The PMC-BiSerial-S311 will be used with a PCI2PMC and Windows NT driver to provide an S311 interface within a PCI chassis.
6/2002 Developments: PCI_Altera_485
Program your own Altera 10K200E or 10K130E from the PCI bus. 40 - 20 MHz. RS-485 IO and 12 TTL IO are provided via D100 connector for IO. Spartan II and PLX 9054 provided to manage DMA on PCI bus. 16 - 4K x 8 FIFOs between Altera and Xilinx. One 1K x 32 FIFO provided for DMA optimization. Status - Schematic complete. Placement complete. Routing in progress. ETA - July 2002. Boards will be supplied with base Altera implementation, NT compatible loader software [for Altera] and preprogrammed Xilinx.
5/2002 Developments: PCI3IP
PCI - Industrypack adapter - updated to have an optional minimized memory map. The memory space was decreased to match the ID, IO, and INT memory requirement. Only 2K bytes requried on the PCI bus. Prior purchased hardware can be upgraded with our PROM upgrade program. Please e-mail sales@dyneng.com .
4/2002 Developments: IP-QuadUART
The IP-QuadUART provides 4 UART channels on a single IP card. The channels are supported by 128 byte FIFOs and programmable RS-232 / RS-422 IO. Multiple baud rates are supported up to 2 MHz.
3/2002 Developments: PCI3IP
PCI - Industrypack adapter - updated to include new static and dynamic address 32 <=> 16 bit data conversion [PCI <=> IP]. Prior purchased hardware can be upgraded with our PROM upgrade program. Please e-mail sales@dyneng.com .
2/2002 Developments: PCI5IP
PCI - Industrypack adapter - Use a PCI card slot to mount your time tested IP module designs. 5 IPs in one slot. 8/32 MHz selectable per slot. Release date 3/15/02
1/2002 Developments: PMC2PCI
PMC - PCI adapter - Use a PCI card for development or production in a PMC slot. Save time and money with existing PCI cards when a PMC version is not available. In Stock
1/2002 Contract award: Embedded PC design: for special data processing application. P3 with SDRAM, FLASH, Ethernet, local PCI, and Xilinx based data filtering and control functions.
1/2002 Developments: pciBpmc
PCI Bridge PMC adapter - All of the benefits of our PCI2PMC design plus a PCI bridge to allow multiple PMC's to be installed per PCI bus segment. On board 7A 3.3V power supply, user selectable logic level [3.3 or 5V], Pn4 IO is accessible and PMC Bezel is mounted through the PCI Bezel. In Stock
1/2002 Developments: IP-Compact Flash
IP-CompactFLASH - CompactFLASH to IP Module bridge. Meets IP electrical and mechanical requirements. CompactFLASH connector on board. IO connector pinned out for IDE interface to allow a second CompactFLASH or other compatible hardware to be connected with a transition module. In stock.
11/2001 Developments: PCI LVDS 8T
PCI LVDS 8T : Dynamic Engineering successfully tests transmission between 8T and 8R designs. 64 Mb of data was transmitted across 8 channels simulataneously. The data was DMA transferred into the 8T, transmitted to the 8R and then DMA transferred from the 8R back into host memory. The received data was checked. The test was repeated in a loop with no errors. The test was run for 24 hours. Development work continues on the 8T driver and additional hardware testing. The second production order for 40 of the 8R boards was received.
10/2001 Developments: PCI LVDS 8R
PCI LVDS 8R : Dynamic Engineering completes the PCI LVDS 8R. The PCI LVDS 8R features 8 high speed LVDS channels which can receive and store data into 512 mB of on board SDRAM. The data can then be moved to host memory with scatter gather DMA. NT driver available. Custom digital data filtering available.
07/2001 Developments: PMC BiSerial Navy
PMC BiSerial Navy : Dynamic Engineering updates the PMC BiSerial to perform Manchester encoding and decoding for a USN program. Redundant transmit and receive channels
06/2001 Developments: PMC 4U
PMC 4U : Dynamic Engineering designs the PMC 4U to provide 4 UART channels plus Z85C30 Serial Communications Controller. Multiple IO standards supported including RS485, RS232, RS423, and RS188.
05/2001 Developments: PIM-Universal-IO
PIM-Universal-IO : Dynamic Engineering designs the PIM_Universal_IO to facilitate rear panel IO in cPCI based systems using PMC's. The PIM_Universal_IO provides the PMC front panel IO where rear panel IO is desired.
04/2001 Contract Award: PCI_LVDS_8T
PCI_LVDS_8T: Dynamic Engineering awarded 2nd design contract for a PCI card with 8 channels of LVDS output, digital filtering and storage. This board has up to 512 mb of SDRAM and scatter gather DMA capability.. ..
04/2001 Product Release: PMC PIM Module PIM modules now available for shipping
The PMC PIM's are 1/2 sized PMC cards mounted onto a PIM carrier board to allow for rear panel I/O. The PIM's can be used with any PMC card. This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891.
03/2001 News from Dynamic Engineering
* Navy contracts with Dynamic Engineering for Manchester design.
* IP-Crypto KYK-13 interface completed
03/2001 New Product Release - IP Parallel-BA1 "IP Tape"
Customer accepts protype - production units are in route to customer. The IndustryPack compatible IP-Parallel-IO board adds 48 channels of IO in one slot. Perfect for embedded control. All registers are read-writeable. Mezzanine boards. This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891.
View our other Industry Pack cards here: Industry Pack cards by Dynamic Engineering
02/2001 Dynamic Engineering Design Awards:
* Contract awarded to design PIM module for Teraburst.
* Contract awarded to design PMC-4U
02/01 New Product Release - S_A_Relay
Allows undetectable active monitoring and data altering of two ethernet (RJ-45) lines.
02/2001 New Product Release - IP BiSerial-RTN2
RTN2 is an update to the IP Biserial-BA2 with an expanded word counter, 16 Mb FIFO, programmable parity odd/even and on/off, programmable almost empty and programmable almost full interrupt capabilities added. IP, oscillator or user clock reference with 12 bit programmable divider for transmit frequencies. This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891. View our other IP Biserials cards here: IP BiSerial versions by Dynamic Engineering
11/00 New Product Release - IP Parallel IO
IndustryPack compatible IP-Parallel-IO board adds 48 channels of IO in one slot. Perfect for embedded control. All registers are read-writeable. Mezzanine boards, VME, PCI, and custom architectures are supported. I/O and embedded control are our specialties.
This product can now be ordered through our sales office: sales@dyneng.com (831) 336-8891.
11/00 - Dynamic Engineering Design Awards:
* Contract to design specialized Parallel I/O IP [IndustryPack] module.
* Network Physics awards contract to design ethernet relay bipass card and offset PCI extender
* Raytheon awards contract to design modifications to our IP BiSerial card.IP BiSerial
* Contract to design specialized BiSerial IP module with negative voltage output.
Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements
11/00 - PCI2PMC Initial Production run sells out in 30 days. The PCI2PMC adapter card allows the user to install a PMC card into a standard PCI slot. Dynamic Engineering has experienced exceptional response on this product and is currently accepting orders for our next production run.
10/00 - PCI_LVDS_8R: Dynamic Engineering awarded design contract for a PCI card with 8 channels of LVDS input, digital filtering and storage. This board has up to 512 mb of SDRAM and scatter gather DMA capability....
9/26/00 - PCI2PMC released The PCI2PMC
adapter card allows the user to install a PMC card into a standard PCI slot. The PCI2PMC has a PMC card slot mounted to a universal 1/2 length PCI card. Suitable for 32 bit or 64 bit bus operation. The PMC user IO connector Pn4 is brought out to two connectors for access (DIN IDC and SCSIII compatible). The PMC front panel connector is mounted though the PCImounting bracket. For superior performance, the PCI bus is buffered with10 ohm series resistors, clamped with Schotky diodes, and the PCI clockis distributed with a zero delay buffer. The PCI2PMC design is passive with no added delays to access the PMC hardware.
9/4/00 - PCI3IP updated A Watch Dog
timer function has been added to the PCI3IP design. The Watch Dog timer
will allow software to read from slots with broken or non-existent IPs without
hanging the PCI bus. Useful to find the top of memory, installed or not,
and protect against failures. The Watch Dog timer provides status and
an optional interrupt to the host to communicate the bus error condition.
7/11/00 - MacPortable Designs
Sold We have sold our Dynamic Engineering line of MacPortable Designs
to Houlton. Thank you for the many years of support our MacPortable
products. Please visit the Houlton page for continued service of your MacPortable
5/01/00 - New revision of BiSerial New
revision of BiSerial New version of BiSerial with 4 transmit channels.
Designed for Photo-Sonics.
4/01/00 - Design win awarded today from Lockheed for an IEEE extender
card re-design.
3/01/00 - Design win Awarded today from Entone - PCI based
ATM design featuring the Intel 80960RN, Fujitsu Firestream and PMC PHY,
128 Mb SDRAM, 4 Mb SRAM, FLASH, and a smart card reader.
2/25/00 - VME Interface Dynamic Engineering was awarded a
design contract by TRW for the design of a VME based telecommunications interface.
The VME [6U] ATM interface with E1 and E3 capabilities will feature a PMC-Sierra
PHY, Altera FPGA(s), and Dallas framers.
2/10/00 - PMC-BiSerial First shipment
of PMC-BiSerial hardware to SED Systems...14 units of the new design were
shipped to the customer today along with the PMC-BiSerial engineering kit.
2/1/00 - PMC-BiSerial Dynamic Engineering
Announces High Performance Differential Serial Interface Ben Lomond, CA,
February 2000 - Dynamic Engineering has announced the PMC-BiSerial-IO,
a high performance Bi-Directional Serial interface on a single-wide PMC module.
The PMC-BiSerial-IO is designed for embedded telecommunications, network
access, data communications and control applications that require high-speed
data throughput. The PMC-BiSerial-IO is available now.
The PMC-BiSerial-IO includes 16Kbytes of transmit and 16Kbytes of
receive FIFO which allows back-to-back transmission with minimum interface
latency. The memory is organized as 32 bit words. The State machines and
memory blocks are fully independent allowing concurrent transmission and
reception. The base design is optimized for long transmissions with programmable
interrupts based on FIFO capacity and transmission or reception completion.
The PMC-BiSerial-IO has 20 programmable differential transceivers with
programmable termination to support custom applications. PMC-BiSerial for more information.
Dynamic Engineering has been very successful with the IP-BiSerial
providing custom interface solutions to a wide variety of companies.
[ IP-BiSerial] Dynamic Engineering welcomes custom
interface requirements with the PMC-BiSerial-IO. The Xilinx FPGA is designed
to be customized quickly for specific customers needs. Dynamic Engineering
expects the -IO version to be the first of many implementations for the
PMC-BiSerial.
1/6/00 - New version of BiSerial released [-LS1] New version of BiSerial with 4 Mhz Data, Clock, Strobe interface 16K FIFO. Designed for DERA / Land Systems
Part Number:IP-Hardware
Ordering Options
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IP-Connector-Saver: Comes with 2 Connector Savers plus 4 standoffs and mounting screws. Add .534" air gap between the installed module and carrier.
Other related models: IP-Debug-Bus is a test aparatus installed between the carrier and IndustryPack to allow the control / data signals to be monitored, hot swapped etc. , IP-Debug-IO is an adapter for the IP Module IO connector. Mates with the IndustryPack connector on one side and ribbon cable on the other. Ribbon Cable 50 pin can be used to connect to the IP-Debug-IO and your system or perhaps finish it off with HDRterm50 which converts 50 pin ribbon to screw terminal.
Custom Length SCSI Cable
Send us an e-mail - sales@dyneng.com with your requirements. Be sure to include the length, retention [clip / screw], and quantity. Please be aware that custom lengths will take several weeks to process. Pricing is quantity sensitive.
HDRterm50 Additional Information
Reference Statement of Volatility