PCI5IP

If you want to use IndustryPack® modules with your PCI system then PCI5IP is the choice for you. PCI5IP combines features you need with simplicity and speed. Up to 5 IP modules can be installed. 32 bit and double wide modules fit right in. Each slot has independent operation - control, clocking, IO, power filtering and protection. PCI5IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result the PCI5IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows 10 or Linux drivers operation can be "plug and play". PCI5IP is a mature design recently updated to revision 12 on the PCB. Thousands shipped and still in operation. Dynamic Engineering launched PCI5IP in 2002 and still supports today. Industrial Temperature components standard. Our base drivers are written to support both PCIe and PCI based IP carrriers allowing our IP drivers to be common for both bus types. This means an IP driver developed for PCI5IP will work with PCI3IP, PCIe3IP, PCIe5IP, cPCI2IP, cPCI4IP, VPX2IP, PCI104-IP etc. For newer platforms requiring PCIe please consider PCIe3IP and PCIe5IP designs.

Our customers are our best source of feed-back and new ideas to implement. A client suggested update to the design of the PCI5IP was to tag all accesses from the PCI bus. IP Modules can take longer than the PCI response specification leading to the use of retry cycles on the PCI bus. In a single CPU system the retry accesses are done serially. The current IP access will be the correct one to respond to the retry access. In a multi-CPU system it is possible to get out of sequence accesses, and potentially have the IP response sent to the wrong retry access. By storing the PCI parameters for the IP access and only responding to the correct retry cycle; multiprocessor cross contamination is avoided. With revision 07 fabs PCI5IP has FLASH instead of PROM´s for better manufacturabilty, reliability and field support.

Multi-board operation is supported. With multiple PCI5IPs in your system and unique cabling, sensors etc. for each slot on each PCI5IP it is important to "know" which PCI5IP is which and to properly control the IP modules mounted to them. A surface mount "dip switch" is provided to create a programmable identifier to the software. A specific PCI5IP can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus. The Dynamic Drivers make use of the Switch and Slot information to uniquely identify each installed IP and to associate a system "handle" with a particular module.

Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together for the five slots plus the state-machine. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation across the 5 IP´s and the controlling state-machine. A well designed clock distribution is critical for reliable operation.

Each slot has resettable "self healing" fused filtered power. +5,+12, and -12V supported.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. The connector are "wired" 1:1 from the IP IO connector to the Header connector. The Headers are numbered with standard ribbon cable conventions. The traces are matched length, differentually routed and impedance controlled between the IO connector and header for each channel. The fist IP position has options for Right angle through the bezel and vertical connectors. Vertical connectors are provided in the remaining positions. Ribbon cable or discrete wire cables can be interfaced directly with the PCI5IP. Alternatively the HDRterm50 can be used to create a terminal block interface. The right angle connector in position A comes with ejectors, and an ordering option for ejectors for the remaining positions is available. This is not the default option due to PCI height restrictions. A recomended upgrade if your system has the room. "-EJ" The front panel can be supplied with a blank bezel or the ribbon cutout version. Please order "-BB" for the blank option. The ribbon cutout versions is required for the right angle connector configuration. A full list of ordering options are available toward the end of this Dynamic Data Sheet.

Slots B/C and D/E are configured to accept two single IPs, or a double wide Industrypack compatible design. Slot A is available for single IP´s. The data bus is designed to allow for 32 bit IP Bus operation. The data bus width is controlled by the address range the slot is controlled with. Automatic switching makes it possible to switch data bus size without changing the control registers for seamless operation.

Three methods of resetting the IP´s are built into the PCI5IP. A local pushbutton reset switch is provided. The switch is accessible between slots C and D. The IP´s can be reset from the control register within the FPGA via the software interface. The IP´s are reset on power-up via a supervisory circuit that guarantees the 200 mS minimum reset requirement in the IP specification. The resets only affects the IP slots.

LEDs are provided to each of the five IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s [3] are provided on slot C. An additional eight user LEDs are available for debugging or other purposes.

IndustryPacks are usually 16 bit devices and the PCI bus supports 32 bits. PCI5IP accepts 32 bit PCI accesses and converts them into two 16 bit accesses with an auto-incremented or static address. One PCI access can be used to write to or read from two IP locations or twice to one location. Byte, Word and Long Word accesses are supported to the 16 and 32 bit IP sites from the PCI bus. If a 32 bit IP has been installed then direct 32 bit operation can be utilized.

The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI5IP is created. The PCI5IP responds normally to the host, not tying up the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences. Multi-threaded software operation is supported with separate bus error status in each of the slot control registers.

The PCI bus is defined as little endian and many IPs have their register sets defined to operate efficiently with a little endian interface. The default settings on the PCI5IP are "straight through" byte for byte and D15-0 written to address 0x00 before D31-D16 written to address 0x02 when long words are written to 16 bit ports. Please note that any long word address can be used. The lower data is written to the lower address first, then the upper data to the upper address. Each slot has a ByteSwap and WordSwap control bit to allow Byte and Word Swapping to be performed to accommodate alternate IP and OS requirements.


Byte Swapping accesses to a 16 bit port.


Byte Swapping access to a 32 bit port

With Rev 07 and later boards the IO routing from each IP module IO connector to the associated box header is done with matched length, impedance controlled, differential traces. 1-2,3-4,..23-24, 25-50, 26-27...48-49. With this pattern the differential pairs can be properly routed for both the IP and Header connectors with adjacent pin pairs used except for the single 25-50 pair. Frequently 25 and 50 are grounds. Routing is still 1:1 as well making signal tracing through the carrier easier to deal with.

With revision 08 and later PCI5IP has been upgraded to incorporate a Spartan 6. 3 new registers are added along with a new feature called "VPWR". VPWR is the voltage on the "5V" connection to the IP modules and terminations. The default is 5V to match the IP standard. The pin allocated to " Reserved 1" is monitored on each IP position and if any are grounded the voltage changes from 5V [open] to 3.3V [grounded]. The VPWR 5V LED is illuminated in open mode and VPWR 3.3V LED is illuminated for the RES1 = GND mode. This feature is being added to all Dynamic Engineering carriers as the transition to Spartan 6 is implemented. Please note: Previous revisions VPWR = 5V independent of RES1.

The benefit of VPWR: Most current FPGAs operate with 3.3V and are not 5V tolerant. To operate on the IP bus level shifters are required on both ends. IP Modules targeting Dynamic Engineering carriers for installation can remove the level shifters and ground the RES1 pin. In addition most IO does not require 5V and can use 3.3V to eliminate a power supply on the IP Module.

Connector positioning is compatible with IP-Debug-Bus to allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI5IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

PCI5IP is an extended temperature board. This extended or "Industrial Temp" design has components rated for -40C to +85C minimum. This temperature range will need to be derated based on your chassis thermal situation.