Now you can use your PMC with a new PC. The new PC´s have PCI Express connectors in larger quantities than PCI slots. The PCIeBPMC ( PCIe Bridge PMC 1 slot) adapter / carrier converter card provides the ability to install one PMC card into a standard PCIe (Express) 1+ lane slot. Suitable for PCI operation with the PMC; 32 bit or 64 bit data and PCI (25, 33, 50, 66) MHz. clock. Auto selected or switch programmable speeds. The bridge can operate with 1 or more lanes active, and can be installed into slots with more than 1 lanes if desired.
Why the Tsi384 instead of the PEX8114? Most current PCIe carriers for PMC are using the PLX PEX8114 device. The Tundra Tsi384 provides significantly better performance. For the details request the Tundra speed comparison document [from Tundra]. It is a confidential document so we can´t reprint the results here.
We can tell you that we ran more than 100K DMA loop-tests using the PMC BiSerial III MDS1 as a test bench. We ran the test for 54 hours and could have left it longer.... The DMA loop uses a message size of 1Mb, significantly larger than the 1K x 32 FIFO within the
MDS1 design. HW moves the data between FIFO´s. DMA moves the data back again. The FIFO´s are relatively small when compared to the file size being transferred. The TX and RX side have independent DMA controllers on the MDS1. There are 4 channels per MDS1. The hardware starts transferring the RX side as soon as there is data in the RX FIFO. The result is that data is being transferred in both directions using DMA across the PCIe bus. The transfers will be somewhat asynchronous to each other creating all possible conditions when allowed to run for an extended period of time.
The hardware ran Friday - Monday without error. The test operates faster than in a standard PCI slot. When you do the math an impressive amount of data was transferred and checked [4+ MLW/S]. The transfer rate is limited by the external IO rate in this case. With standard PMC [PCI 32/33] approximately 16 MLW/s can be sustained. With the local HW set to 50 MHz more than 20 MLW/S
Faster, lower powered, less complex power supply requirements, higher MTBF. In short, a better product. We use PLX devices on a number of our designs. In this case the Tundra part is superior. If you care about performance, when comparing PCI Express carriers check for the Tsi384 bridge.
The PMC user IO connector Pn4 is available on a SCSI II connector. The Pn4 "user IO" is routed differentially with matched length and impedance control to the SCSI connector. The PMC front panel connector is mounted though the PCIe mounting bracket.
For superior performance, PCIeBPMC has dual cooling cutouts for increased airflow to the PMC. If your application requires a fan you can order
PCIeBPMC-FAN to have a fan(s) mounted to your PCIBPMCX1. The FAN positions are numbered 1-2 with 1 closest to the PCIe Bezel [left edge in the picture above]. Both fan positions can be mounted. Both positions are in "legal" PMC locations and can have a "Zero Slot Fan"™ mounted where the fan does not take any extra slots. Higher volume fans can be rear mounted and potentially require an extra slot.
The PCIe bus is interconnected to the PMC via a bridge. The bridge can operate with 1, 2, 3 or 4 lanes in operation. Only lane 0 is connected on the PCIeBPMC design. For 4 lane PCI-X speed capability use the
PCIeBPMCX1. LED´s are provided to indicate the Lane status. The Secondary side of the bridge can operate with 32 or 64 bit data PCI . The design uses a DIPSWITCH to allow selection of auto or force on the clocks. With Auto the PMC PCIXCAP and M66En signals are used to determine the clock speed. With Force, the DIPSWITCH is used to select the clock rate. The buffering within the bridge will take care of the rate and data matching. The local side can also operate at 66 or 33 MHz depending on the PMC´s installed.
The voltage definitions are buffered between the PCIe and PMC buses. PCIe is fixed LVDS levels, and the PMC VIO is set to 3.3V.
The bridge is located near the PCIe "gold fingers" and routed with PCIe specification compliant traces for impedance and length to insure maximum performance from your Express system.
The -12V, 5V, and 3.3V for the PMC are regulated on board. The power supply designs utilize switching regulators controlling a MOSFET to convert 12V. An LC filter insures clean power at the PMC. The bridge uses a small amount of 3.3 plus 1.2V which are supplied by the PCIe 3.3V supply. The PCIe gold fingers are rated for 1.1A each, and a total of 5.5A on the +12V rail. 55W are available to the card after power conversion. Please note this is the combined power requirement across the +12, -12, +5, and 3.3V power used by the PMC. In most cases 55W is sufficient. PCIeBPMC has a cable connector to allow additional 12V power to be added to the card. The two supplies are DIODE coupled. In some cases the 12V supply on the backplane will not be adequately routed by the PC causing voltage sag on the 12V. If this occurs use the cable connector to compensate.
The power supplies include the bulk capacitance to properly bipass the FET´s and post conversion voltage rails. In addition the PMC connectors are bipassed with a .1 uF capacitor at each power pin. The power supplies are checked with voltage monitor circuits. The LED´s are not illuminated unless the voltage is within the defined range.
The individual pins on the JN4 (PN4) connectors for each slot are accessible by a 68 pin SCSI connector. We recommend using our SCSI cable and the
HDEterm68 breakout block with the SCSI connector.
The PMC JTAG connections are routed to a header. The header is configured to for discrete connections. Please add -JTAG if you want the header installed on your PCIeBPMC.