VPX Receiver Controller

VPX Receiver Controller

VPX Receiver Controller Simplified Block Diagram
VPX Receiver Controller is a 3U 4HP design that can be used for many purposes. The primary design implementation is to act as the controller slice within a digital receiver. The host computer can access the Receiver Controller over the PCIe bus within the VPX system or using the SPI bus available from P2. The Receiver Controller buffers commands from the host and converts them to the appropriate format to interface with the rest of the Digital Receiver. The initial design is controlled with several SPI [Serial Peripheral Interface] and SMB buses.

The host SPI connection to VPX-RCB is augmented with a 3 bit parallel address and master enable signal. The address bits allow VPX-RCB to determine the destination to be driven or read. Data is automatically redirected to the end point and enables asserted to support the transfer. In the case of the SMB connections VPX-RCB automatically converts the full duplex SPI bus into the half duplex SMB protocol. Addressing embedded within the SPI traffic allows direct control of the local devices. The internal [FPGA] registers are dual accessible to allow the PCIe bus to interact with these as well. Each of the SPI buses is controlled within the FPGA and separately buffered with 24 mA LVTTL line drivers. The FPGA logic is programmable to allow new definitions for each of the SPI buses or new buses altogether.

The Receiver Synthesizer and Calibration Source interfaces are supported with a total of 4 SPI buses controlled by the host and buffered by the VPX-RCB. The DAC uses an SPI bus to program the channel and value to output. The monitor circuits are on the SMB and provide temperature, voltage, and Fan speed information. The internal and several external voltages are measured.

The DAC is implemented with an 8 channel device. Each channel has an inverting buffer. The output swings from 0V to minus 3V to control the attenuators within the receiver. The 8 attenuators are available on the 69 pin high density connector at the front panel. The DAC is tasked with the SPI bus. The host selects the channel it wants to convert. Individual channels and groups of channels can be set in parallel. The DAC is centered in the photo with the opamps to the left. The pin definitions on the communication connector are designed to allow the analog ground reference to cover the attenuation signals from the DAC through the opamps and to the connector. Please refer to the HW manual for the pinout.

Two Texas Instruments LM81s are used to measure the local temperature on the surface of the board as well as provide the voltage monitoring and fan measurement functions. Please see the HW manual for details of the voltages measured and the scaling used.

Three SSMA connectors are supplied with a 10 MHz clock reference. The signal is LVTTL. The reference for the 10 MHz can be from an external reference or from the local TCXO. A dual counter is provided with control from SW to capture a known count with the internally generated 10 MHz and the external 10 MHz for comparison purposes - signal present and accuracy. The limits of the acceptable counts for the time programmed can be set. The time is based on the local 100 MHz clock. Status is provided where "good" means above the lower limit and below the upper limit. The tests run automatically. An interrupt is available if the status changes.

LED´s are provided to indicate the PCIe lanes acquired plus basic voltage status. EPADs are also provided to measure voltages and reference frequencies.

Four special purpose inputs are available. The initial use is for Blanking signals which can be single ended or differential, low voltage or high voltage. The four channels have differential signal routing with 1/2 W shunt selectable resistive elements to allow operation from high voltages or low. You can see the circuits basically centered along the lower edge of the board in the photo.The four channels have shunt selectable 100 ohm parallel terminations [can be populated with a different value...] or a digitial pot programmed reference voltage or open. The signal is passed to a high speed comparator [4 channel] with 700 pS delay. The comparator can handle +/-5V signals. The received signals are diode coupled to the power rails to prevent over and under voltage issues. The signals are currently routed through the FPGA and converted to LVDS to be redriven to the P2 connector for the local host CPU. The FPGA can have added signal processing etc. added for these and other signals.

There are multiple LVTTL buffers, LVDS transceivers, and RS-485 transceivers used within the Receiver Controller. The transceivers are programmable for direction and termination. The transceivers are set to the directions required for the initial design and can be modified for other requirements.

The universal PCI interface on the FPGA is 32/33 and can support DMA. The base design is register accessed. The bridge supports both DMA and target access types. SPI control from the host is the expected initial control path

The FPGA is a Xilinx Spartan 3 2000 with plenty of uncommitted gates to expand capabilities, and add new features. The FLASH is set-up to handle a 4000 level device if needed. For example it is planned to add the FPGA CPU capability in the future. Most of the block RAM is available for new functions. Cables, Breakouts, and custom cables available. Detailed Hardware manual [PDF] available for download at the bottom of this page.