PCIe4lHOTLinkx5

HOTLink is used in applications demanding high speed and high reliability including sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. For example the first client project featuring PCIe4lHOTLinkx5 uses the HOTLink interface to capture data from high speed A/D´s.

PCIe4lHOTLinkx5 is a PCI Express card with 5 HOTLink receiver/transmitter pairs. Each of the HOTLink channels is supported with a separate DMA transfer engine plus local memory. All ports are full duplex with the lower 4 connected through a VHDCI connector and port 5 connected though coax connectors [4]. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames [indepedent each channel].

The HOTLink protocol implemented provides positive emitter coupled logic (PECL) or LVDS data inputs and outputs. The transmit byte rate is determined by the programmed frequency of the PLL clock output. This clock is multiplied ten times by the HOTLink transmitter to send the transmit byte data stream which is expanded to 10 bits by the internal 8B/10B encoder. The PLL is programmed via software over a serial I2C interface.

Up to five independent HOTLink channels are provided per card. The base design implemetation has programmable frame definitions - which K´s are used to start a frame and end a frame. The start and stop are further programmable to be up to 3 K´s in series with the same or different values for each. Interrupt options are provided to support frame capture nad movement to the host memory.

The x5 design is related to the x6 with the main difference being the connectors used, and organization of the ports. Designs on either board can be ported between them.

PCIe4lHOTLinkx5 utilizes a Spartan 6 100 FPGA. The FPGA allows for a lot of internal memory and complex data manipulation in HW. The memory is typically used for FIFO´s or RAM. The FIFO´s can be accessed by single-word [target] read/writes as well as DMA burst transfers. A FIFO test bit in each channel control register enables the data to be routed from the transmit to the receive FIFO for a full 32-bit path providing loop-back testing of the FIFO´s. The channels are supported with 12 independent DMA engines. A local arbitration unit keeps everything moving efficiently. DMA transfers can be programmed for any size transfer from very small to multiple megabytes using the scatter gather capable programming model.

All parts are industrial temp or better [-40C <=> +85C]. Conformal coating, is available to help adapt to your environment.


PCIe4lHOTLinkx5 Block Diagram