PCIe Altera Cyclone IV

User Configurable Logic - PCIe Altera Cyclone IV 485/LVDS comes with everything you need to load your Altera program into the Cyclone IV. Fantastic for development, simulation, special purpose interfaces, multiple serial and / or parallel channels. FLASH and on-the-fly reloading for configurable and reconfigurable logic implementations.


PCIe compatible PCIeAlteraCycloneIV-485/LVDS design is for the advanced user who wants to implement their own Altera design or requires updatable logic. PCIeAlteraCycloneIV makes the implementation, and use of the Cyclone IV easy.

The design comes with the basic features built in and the specific features ready for you. The PCIe-Altera Controller takes care of the PCIe interface for initial loading of the Altera Cyclone IV, and DMA transfer of data into and out of the FIFOs. The Altera FPGA controls 40 programmable RS-485 or LVDS transceivers and 12 TTL IO. Each of the RS-485 or LVDS channels is programmable for direction, termination and function. The IO can be mixed too. The 12 TTL IO can be inputs or outputs. Eight Cypress 22393 PLLs support the FPGA with 24 programmable clock references. The only thing missing is your input in the form of a coprocessor, reconfigurable logic, state-machine, simulated system, asynchronous or synchronous data processing etc.

Software [Windows and Linux] to load the Altera, access the hardware, and run diagnostics is available as well as a reference design for the Altera Cyclone IV which controls the byte lanes, IO, and PLL´s. The drivers come with calls for the standard features plus a generic R/W interface to allow for any user update without needing driver modifications. Many of the reference software files use the generic IO control to show how this is done. We provide a plug ´n play set-up along with our ATP software to give you a running start at your design.

PI7C9X130 is used to bridge between the 4 lane PCIe interface and the PCIe-Altera Controller [Xilinx Spartan 6 FPGA]. Together the bridge and Spartan 6 are used to move data to the Altera for output channels, and to move data to the host for input channels. 8 input and 8 output FIFOs are provided to support 8 bi-directional channels. The intermediate FIFOs are byte wide and operate at 66 MHz between the Spartan 6 and Cyclone IV. Each of the data paths has its own DMA controller and local arbitration to move data from the Altera through the Xilinx to the the PCIe lanes or vice-versa. In addition, a control bus is provided - 32 data, 12 address, 33 MHz to provide a method of programming registers or memory within the User Design. An interrupt request from the Altera through the Xilinx is provided.

IO is accomplished via RS-485 or LVDS transceivers or TTL buffers. The RS-485 transceivers are rated for 40 MHz. The LVDS is rated for 200 MHz. Each transceiver can be controlled for direction and termination. The TTL IO is implemented with ´125 open drain drivers with on-board pull-ups. The input direction is buffered with a receiver to protect the Altera and to provide level shifting between the 5V IO and the 3.3V Altera IO. The D100 [ SCSI II 100 pin connector ] provides an easy to interconnect cabling system. The pinouts are consistent with the industry standard differential pairings. The HDEterm100 supports the D100 with a cable to terminal strip conversion.

An 8 position dip switch is provided. The switch is read through the Controller FPGA. The switch can be used to distinguish multiple PCIeAlteraCycloneIV boards in the same system or for other user determined purposes.

LEDs are provided. 4 are controlled via the Altera and the user design. Others are provided to show the power suppies are within tolerance. The LEDs can be used for debugging or for system status etc.

We can do the design implementation for you, and provide the design files to you for long term support. If you need the features of the PCIeAlteraCyclone IV and prefer to have someone else do the programming, please contact us with your requirements.