PMC-BiSerial 3T20
PMC Compatible Multi Function Interface with transformer coupling



The BiSerial Family has been expanded to include a transformer coupled IO version. The "3T20" has 20 transformers in 10 packages. The transfomers are 1:1 and have several termination options.

The 22 IO can be configured to support one function, one function replicated several times, or multiple functions. With the 2 discrete [direct connect] channels, level controls can be implemented. Also, the transformers can be left off additional channels and zero ohm resistors used to bipass the transformer locations if more direct connect IO are needed. WIth the transformers, continuous output IO types will work best - for example Manchester with an idle pattern. Interfaces that become tristated or left at a fixed value between transmissions can be used and may require an extra edge to occur if the initial transition is masked by coming out of tri-state. Many protocals have this feature built-in - a wake-up pattern of some sort preceding the actual message.

PMC BiSerial 3T20 is recommended for new designs. Many of the implementations already done for the non transformer coupled version can be ported [easily] to this platform. Please see the custom section of this page and the PMC-BiSerial-III page as well. The hardware has been used to interface with a wide variety of equipment. What do you need to communicate with? Control? Capture data from? Please see the bottom of this page for descriptions and manuals for our customerized versions. We have been doing custom versions of the BiSerial since 1998 when the IP version first came out. We will be doing custom versions in the future with the next generation parts and features.

A new custom version can be implemented in a very reasonable time. Typically 1-2 weeks of design time for a medium sized project including the new VHDL set, Windows® driver, reference software package, and documentation. Examples of the designs performed to date are listed toward the bottom of this page. Click here or or scroll down to see if the configuration you need already exists or if we need to work on a custom version for you.

We can be rapid with our response because the designs are structured to allow channels to be moved in and out to create new design sets. Most designs have a fairly large component of reused "known good" VHDL that we can pull from allowing us to focus on the new functions required for your implementation. You are getting the benefit of many man-years of design and test time with each new version created. Join our high reliability clients by taking advantage of our know-how to help speed your project to completion.

If you need conduction cooling the ccPMC BiSerial III Trans is available. For PCIExpress we now have a native version with a DB37 connector. The PMC version can also be used along with a PCIe carrier when more IO is required. Please see the PCIeBiserialDb37.

PMC´s are mezzanine cards designed to be mounted to an adapter / carrier or host. Dynamic Engineering has PMC carriers for PCI, PCIexpress, cPCI, PC104p, VME and can do custom design´s specific to client requirements as well. Please use the handy JAVA pull-down menu at the top left of any page to navigate to other Dynamic Engineering products including carriers.

PMC´s are independently specificed through VITA for the form factor, connectors and pinouts of the PCI signaling; you can use the PMC-BiSerial-3T20 design with any carrier from any vendor that supports standard PMC´s. To make it even easier the PMC-BiSerial-3T20 has a universal PCI design to allow operation with VIO set to 3.3 or 5V.

It all starts with the PCB [Printed Circuit Board]. Quality design and quality materials are required to meet the strenuous requirements of many of our implementations. You can do the job quickly or you can do the design correctly. We pride ourselves on taking the time to put the extra work into our layouts. The quality goes in before the parts go on. In addition to routing strategy and layer counts, Via size, plating requirements, break-out trace widths, and materials are areas where quality comes into play. The via size and method of trace attachment to the via affect the signal shape and reliability. Using tear-drop trace connections to pads, via´s and through hole components enhance the reliability and minimize the impedance discontinuity resulting in a cleaner signal. Using 12 mil vias provides adequate copper for proper power distribution and more surface area to bond to where traces are interconnected. The combination provides better vibration endurance than smaller vias and traces would provide. The design has several power planes with sufficient copper weight and coverage to provide the references required for the routing plus the current and voltages needed by the various devices on the board. The larger features make the design work more difficult since there is less room to "play with" and the end result is worth it. PMC BiSerial III has an excellent track record for reliability. - PMC BiSerial-3T20 is implemented using the same techniques as the PMC-BiSerial-III.

The PCI interface has a published set of requirements for compliance which restrict length, impedance, loading and other factors. PMC-BiSerial-3T20 is compliant with the PCI Specification. The IO section has requirements based on the IO type and the purpose for the IO. A very conservative approach has been taken to allow operation with any client requirement. The IO on the connector side is differential with a 100 ohm impedance requirement. Between the FPGA and the tranceivers the IO is single ended. Each IO has separate direction, termination, and data lines to allow complete flexibilty. The design has matched length connections from the FPGA ball to the seating plane of the connector. The lengths are matched to the "mil". The Impedance is controlled and the signals routed with proper spacing to avoid cross talk etc. The other features including memory, PLL, oscillator, and power supplies are implemented within the PCB to exceed the operational requirements for those devices.

The Spartan III has internal block RAM which can be configured in a variety of ways. Currently, up to 48K x 32 of FIFO can be configured for internal channel memory support. In addition the memory can be configured as Dual Port RAM to allow direct addressing and retransmission of repeated patterns. The HW1 design has 20 channels each with 512 x 32 of Dual Port RAM.

Sometimes you just need more memory. Two external [to the FPGA] FIFO´s are available with 16Mx32 each. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. Internal loop-back is supported. The loop-back test can be used for BIT and for software development. Programmable FIFO flags are supported on both sets of FIFO´s. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any depth to allow software a programmable delay from event to empty or full. The memory is SDRAM based and programable for size as well. Most designs have an Rx and a Tx channel associated with each other as full or half duplex. The boundary for the Tx and Rx portions is programmable. The interface looks like a FIFO providing a simple to set-up and very flexible, very large memory buffer.

Interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling. In addition DMA can be programmed to fill or empty the FIFO with sizes larger than the FIFO size. The DMA will be hardware controlled to be held off when no data is available or no room is available. With the "Channelized DMA"™ capability and large FIFO´s the software application can have reduced interrupt counts to deal with while supporting larger and faster IO transfer rates.

PMC-BiSerial-3T20 has 22 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PMC-BiSerial-3T20. RS-485 transceivers support up to 40 Mhz clock and data rates. The channels 19-0 have 1:1 100 base T transformers installed as the default with channels 21-20 being direct coupled. The transformer channels can be replaced with direct coupled if required. Since there are two per package, the replacement needs to be done in pairs.

The IO is available through the front panel mounted SCSI III connector. Each transceiver pair is isolated from the transformer with resistors. The resistors can have different values installed for different stituations. For example, if the SW selectable switches are used, a low impedance .05 ohm resistor is typically installed. If the switches are not used something approaching 50 ohms is more likely. On the connector side of the transformer an additional parallel termination resistor is available. The external resistor is generally not used with the internal switched resistor.

Clock options are frequently a major factor in embedded designs. Getting the right reference to the right part of the design and allowing for local control of exact frequencies. PMC-BiSerial-3T20 has a PLL with 4 programmable outputs, reference oscillator, internal DCM´s and buffering plus programable dividers instantiated within the VHDL. The PLL can be programmed to "any" fixed frequency, the DCM used to create phase variations, and local dividers to allow on-the-fly channel based frequency changes.

"Channelized DMA"™ is an important feature of the PMC-BiSerial-3T20 design. With "Channelized DMA"™ you have a separate DMA engine for each transmitter and each receiver within each channel. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency.

If your situation demands a custom application we will update the Xilinx FPGA and IO components. Send us your timing and we will send you the interface. Please refer to the bottom of this page for previously completed "customerized" PMC BiSerial 3T20 implementations.
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PMC-BiSerial 3T20 Example Block Diagram

PMC-BiSerial-3T20- HW1 version block diagram
See the bottom of Dynamic Data Sheet for more options


PMC-BiSerial-3T20 Features

Interface Types	Custom programmed interfaces are available. Please send us a timing diagram, and we can program one for you. Most interfaces can be adapted from our large library of designs within 1-2 weeks including the updated VHDL, Windows Driver, reference manuals etc. We can support on-site [ours] integration to help you get your application level software working. Alternatively choose one of the already completed versions and purchase off-the-shelf. Common requested and implemented interface types include: Manchester, Miller, SDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive
Signaling	22 RS-485 / RS-422 / LVDS compatible IO are provided with transformer coupling on up to 20 of the IO. Any combination of transmit or receive channels can be created. LVDS and RS-485 can be mixed. RS-485 bandwidth is lower when mixed [16 Mbps]. Programmable termination.
IO	The IO is available via the PMC bezel connector - SCSI 68 position connector with latch block or thumbscrew style retainers. The differential IO is properly routed with impedance control, pitch, and space plus matched lengths across all of the pairs.
IO Speeds and Clocking	Up to 40 MHz RS485, and up to 100 MHz LVDS signaling supported [with transformers installed. The upper frequency for the LVDS in direct connect positions is greater than 200 Mhz. 4 channel software programmable PLL. Reference oscillator. Counters / Dividers / DCM for local clock control.
PCI Speed	PCI 33 MHz. operation Standard Target accesses, and "Channelized DMA"™ supported. "Channelized DMA"™ is a full DMA capability on each function in a multi-function implementation. Standard 32 bit operation supported.
Software Interface	PMC registers are read-writeable. Linux and Windows® drivers available. Design help for alternate OS implementations.
DIP Switch	An 8 bit "DIP Switch" is provided for user purposes. The DIP switch can be used to allow the application software to positively identify a PMC-BiSerial-3T20 in a multi-board implementation. The PCI bus enumerates the address which means the application software can´t rely on the address to always match up with a particular card. With the DIP switch the particular BiSerial can be identified and postive control over a particular asset provided. Could be important depending on what you are connected to. The switch can also be used for software control, a debugging aide or other user purposes.
Interrupts	Software programmable interrupts on status, errors, completion of transfer, DMA, FIFO levels, custom events. Status can be polled for non-interrupt driven operation as well.
Memory	Separate FIFO´s / Dual Port RAM are provided for all channels. Internal FPGA Block RAM memory modules for fast access. Optional discrete FIFO´s -16M x 32 are available.
FPGA	Xilinx Spartan III 2000 and 4000 models are installed based on client requirements. FLASH is used to program the FPGA. In many cases any feature updates can be sent to your facility to reprogram without down time.
Power	+5 and 3.3V. 2.5V and 1.2V converted with on-board power supply.
Temperature	Commercial Temperature is standard. Industrial [-40 <=> +85] is available.
Assembly	Standard [leaded] processing or ROHS compliant processing are available. See ordering options.
Conformal Coating	Conformal Coating is available to support operation in condensing environments.
Size	Standard Single PMC

PMC BiSerial 3T20 Benefits

Speed	PMC-BiSerial-3T20 is optimized for differential interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the PMC BiSerial has independent channel functions. Channels can operate at maximum rate in parallel. With the Spartan III "Channelized DMA"™ can be implemented and still have plenty of gates left for your application.
Price	PMC-BiSerial-3T20 is easily programmed to implement new functions. Many previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. a modified PMC-BiSerial-3T20 will represent a large cost savings in your budget. With our large and growing VHDL library your function(s) may be close to complete when we start since we can modify existing implementations or repackage them as required.
Ease of Use	PMC-BiSerial-3T20 is easy to use. The registers are designed to be R/W without layering or other indirect control methods. Use the Dynamic Driver with Windows® or Linux or create your own. The HW manual has the full address and bit maps plus definitions for each function. In most cases the interfaces are "Point and shoot" - just fill the FIFO and set the start bit to get your custom protocol transmitting. The driver and user application reference software have built in utilities for parsing new PLL frequency files, loading the PLL, reading the switch, doing loop-back using DMA via the IO and between FIFO´s. Built in loop-back capabilities and engineering kits help with integration into your system. We can write a custom Windows® or Linux driver for you.
Availability	Dynamic Engineering works to keep the PMC-BiSerial-3T20 in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with the another version then send updated FLASH Files later to help get your project going - right away.
Size	PMC-BiSerial-3T20 is a standard single wide PMC card, and meets the PMC mechanical specifications. Referring to the photo above, the first 6 transformer packages [12 transformers] are completely within the PMC "connector area". The remaining 4 packages are almost completely within the legal area but do protrude into the IC area slightly. The transformers are slightly taller than the 4.7 mm allowed for the component area. If your carrier has components up to the boundary please refer to the manual for a detail of the height restriction imposed on the carrier. In the worst case 12 channels can be populated. All Dynamic Engineering carriers can be used with the full complement of transformers, including those with "Zero Slot Fans" in the first position.
PMC Compatibility	PMC-BiSerial-3T20 is PMC compliant per the IEEE 1386 specification with the caveat for the height as noted above.
PCI Compatibility	PMC-BiSerial-3T20 is PCI compliant. You can develop with a PCI /PCIe to PMC adapter - PCIeBPMCX1 or PCIBPMC. Use the Java pull-down menu´s for more carrier options.

Engineering Kits
General Descriptions: The SW options are shown with each model below. The reference software included in the User Application is provided in source form and is a complete project including calls to the driver to perform card functions, board identification from the system, a simple and powerful test menu etc. The driver is provided as .SYS and .INF files for Windows® and source for Linux.

PMC-BIS-III-ENG-1
Engineering Kit for PMC-BiSerial-3T20 includes: Board level Schematics [PDF], Reference Software [WIN XP/2000 Driver Visual C ZIP file and or Linux Tar file], HDEterm68-MP, HDEcabl68 customized for the version of PMC-BiSerial-3T20 you are interested in.


Customer Special Versions & Manuals
You can order these too or request that we design one for you

PMC BiSerial 3T20 version HW1
Customer: The Goebel Company
The HW1 protocol implemented provides 20 Manchester encoded data channels per card. Each channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 20 channels.
Download the HW1 Hardware manual
Download the HW1 Windows® manual, Please note: this manual is in common with the PMC-BiSerial-III-HW1



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PCIBPMC bridged PCI to PMC adapter card
PCIBPMCX1 bridged PCI(x) to PMC(x) adapter card with matched length differential routing from Pn4 to SCSI connector
PCIBPMCX2 bridged PCI(x) to PMC(x) adapter card with two PMC positions
PCIeBPMCX1 bridged PCIexpress to PMC(x) adapter card with matched length differential routing from Pn4 to SCSI connector
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cPCIBPMC3U64 bridged cPCI to PMC adapter card 3U 4HP
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cPCIBPMC6UET bridged extended temperature cPCI to PMC adapter card 6U 4HP 2 PMC positions
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PMC MC X4 PMC Mini Carrier with 4 PMC positions. Chassis available


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