PCI3IP

IndustryPack® Modules are an important part of solutions for Embedded situations. Rugged, small, light ... just right for many applications. IndustryPack® Modules require a carrier to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats. PCI3IP is designed to support PC computer based solutions. Solutions available for PCIe, PC104p, cPCI, and VPX, with plans for for cPCIexpress, PC104express.

If you want to use IndustryPack® modules with your PCI system then PCI3IP is the choice for you. PCI3IP combines features you need with simplicity and speed. Up to 3 IP modules can be installed. Each position has independent operation - control, clocking, IO, power filtering and protection. PCI3IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result the PCI3IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows 10 or Linux drivers operation can be "plug and play". PCI3IP is a mature design recently updated to revision 10 on the PCB. Thousands shipped and still in operation. Dynamic Engineering launched PCI3IP in 1999 and still supports today. Industrial Temperature components standard. Our base drivers are written to support both PCIe and PCI based IP carrriers allowing our IP drivers to be common for both bus types. This means an IP driver developed for PCI3IP will work with PCI5IP, PCIe3IP, PCIe5IP, cPCI2IP, cPCI4IP, VPX2IP, PCI104-IP etc. For newer platforms requiring PCIe please consider PCIe3IP and PCIe5IP designs.

PCI3IP is part of the IP Compatible family of modular I/O components. PCI3IP provides three IndustryPack® module sites in one PCI position. PCI3IP acts as an adapter, converter, carrier, and bridge between the PCI bus and your IndustryPack® hardware. PCI3IP is a half size, 32/33 PCI card compatible with the smallest chassis and all PCI slots.

PCI3IP is supported with Windows® compliant WDF drivers for Win10 etc. as well as Linux. The drivers come with a generic IP driver to allow use with "unknown" IP´s <=> IP´s that do not have a driver designed yet. For example, third party IP´s.

IndustryPacks are 16 bit devices, and the PCI bus supports 32 bit accesses. PCI3IP accepts up to 32 bits, and converts as required. Most modern CPU´s can generate 8, 16, and 32 and 64 bit transfers. The IP accesses can be auto-incremented or static address accesses. With the static access option the intended word can be accessed multiple times. With auto-incremented addresses multiple addresses are accessed. PCI3IP provides the capability of handling l32 bit words to reduce the average execution time. By changing from 16 bit accesses to 32 the overhead is cut in half leading to much higher bandwidth.

The Dynamic Engineering implementation does not require any special features on your IP module. Larger transfer sizes are especially useful for repetitive data transfers - loading or reading from RAM or FIFO´s faster will reduce the overhead on your CPU leading to more available time to process the data leading to lower cost or more capable systems.

Each position has a separate clock controller for 8 and 32 MHz operation. The frequency to be changed on the fly. The state-machine within the bridge design automatically locks to the IP Slot frequency as programmed.

PCI3IP is to tracks all accesses from the PCI bus. IP Modules can take longer than the PCI response specification leading to the use of retry cycles on the PCI bus. In a single CPU system the retry accesses are done serially. The current IP access will be the correct one to respond to the retry access. In a multi-CPU system it is possible to get out of sequence accesses, and potentially have the IP response sent to the wrong retry access. By storing the PCI parameters for the IP access and only responding to the correct retry cycle; multiprocessor cross contamination is avoided.

Each IP position has "self healing" fused, filtered power. Each IP Module has separate bulk and bypass capacitance.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. Vertical connectors are provided in the rear two positions. The connector at the bezel is a right angle model and is mounted through the bezel. The bezel connector is outfit with ejectors. An ordering option for ejectors to be mounted to the rear vertical headers is available. This is not the default option due to PCI height restrictions. A recommended upgrade if your system has the room. "-EJ"

The bezel has a cut-out to allow the ribbon cables to be brought outside of the chassis without requiring an extra slot in the chassis. The blank bezel is available by adding "-BB" to the part number.

Ribbon cable or discrete wire cables can be interfaced directly with the PCI3IP. Alternatively the HDRterm50 can be used to create a terminal block interface.

The IP´s can be reset from the control register within the FPGA via the software interface. In addition at power-up the IP´s are provided the 200 mS reset as required by specification.

LED´s are provided to each of the three IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s are provided using voltage monitors. An additional eight user LED´s are available for debugging or other purposes.

A surface mount "dip switch" is available for configuration control or debugging purposes. The switch values are available to be read via the PCI bus. The switch is used for deterministic control by the driver. When multiple carriers are used in the same system the switch is used to allow the driver and application software to "know" which carrier maps to which handle. Further the slot information for a particular IP is stored to create a "vector" pointing to a specific slot on a specific carrier. Deterministic control of specific interfaces is easily achieved with this system without hardwiring system data into your software. The application software will be more portable and not break when new assets are added to the system (and your PCI addresses change).

IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI3IP is created. The PCI3IP responds normally to the host, not creating an errror on the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences.

Connector positioning is compatible with IP-Debug-Bus will allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI3IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

PCI3IP has an alternate "mini-map" option available. The standard design provides the full address space to the IP Memory space. The mini-map provides a minimized memory space equal to the ID, IO, and INT spaces with 128 bytes. The total PCI memory space is reduced to 2K with this option. Please download the alternate manual to get the address map and other details. Please order with the -MM option for the mini-map.

PCI3IP is an extended temperature board. This extended or "Industrial Temp" design has components rated for -40C to +85C minimum. This temperature range will need to be derated based on your chassis thermal situation.

With revision 11 and later PCI3IP has been upgraded to incorporate a Spartan 6. 3 new registers are added along with a new feature called "VPWR". VPWR is the voltage on the "5V" connection to the IP modules and terminations. The default is 5V to match the IP standard. The pin allocated to " Reserved 1" is monitored on each IP position and if any are grounded the voltage changes from 5V [open] to 3.3V [grounded]. The VPWR 5V LED is illuminated in open mode and VPWR 3.3V LED is illuminated for the RES1 = GND mode. This feature is being added to all Dynamic Engineering carriers as the transition to Spartan 6 is implemented. Please note: Previous revisions VPWR = 5V independent of RES1.

The benefit of VPWR: Most current FPGAs operate with 3.3V and are not 5V tolerant. To operate on the IP bus level shifters are required on both ends. IP Modules targeting Dynamic Engineering carriers for installation can remove the level shifters and ground the RES1 pin. In addition most IO does not require 5V and can use 3.3V to eliminate a power supply on the IP Module.