IP-Parallel-IO Block Diagram
The IndustryPack® compatible IP-Parallel-IO with counter and timer design provides 48 digital parallel IO lines in one IP module slot of your carrier board. These IO´s can be configured to be TTL or RS485 compatible in several combinations. A real space saver for systems with both types of IO. Perfect for your embedded control applications. Please download the manual [see bottom of page] for more information. IP-Parallel is available as an add-on IndustryPack Module for use with carriers on all of the common buses: VPX, VME, cPCI, PCI, PCIe, and PC104p. IP-Parallel is supported for both Windows® and Linux.
The IP Module driver can be instantiated multiple times to control multiple cards by the same CPU. IP-Parallel-IO when coupled with the Dynamic Driver "knows" what slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right card. The IP Driver can determine which type of IP-Parallel is installed and load the correct driver. All 7 types of the base design are supplied with the IP Parallel Windows® driver.
PCIe implementations are supported with the
PCIe3IP and
PCIe5IP.
Applications from 1 to 240 TTL lines and/or 1 - 120 Differential pairs per PCIe slot.
PCI implementations are supported with the
PCI3IP and
PCI5IP.
Applications from 1 to 240 TTL lines and/or 1 - 120 Differential pairs per PCI slot.
cPCI 3U is supported with the
cPCI2IP. Applications from 1 to 96 TTL lines and/or 1 - 48 Differential pairs.
cPCI 6U is supported with the
cPCI4IP. Applications from 1 to 192 TTL lines and/or 1 - 96 Differential pairs.
PC104p is supported with the
PC104pIP. Applications from 1 to 48 TTL lines and/or 1 - 24 Differential pairs.
PC104p situations with a custom mechanical can be done with the
PC104p4IP.
Channel counts from 1 to 192 TTL lines and/or 1 - 96 Differential pairs per PC104 stack position.
IP-Parallel-485 Block Diagram
Each channel is programmable to be an input, or an output on a channel-by-channel basis via software. All DIO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered. The registers are mapped as 16 bit words. All control registers are read-writeable.
Outputs in TTL mode are driven with 24 mA open-drain devices to allow multi-drop applications. 470 ohm pull-up resistors are provided. In 485 mode individual transceivers provide direction control and RS485 compatibility.
An external oscillator position is provided for custom applications.
IP-Parallel-IO IO Filter and Interrupt Control Block Diagram
Frequently it is necessary to correlate the time and the event. The IP-Parallel design supports an enhanced MC68230 capability with two - 32 bit counter - timers. The counter-timers are easy to use with a minimum of registers to access and complete independence. The IP clock is used as a reference; both 8 and 32 MHz can be used.
Counter/Timer A features a 32 bit down-counter with a pre-load register. The counter output is tested against a "zero" value. When zero the counter is re-loaded with the pre-load value to create a cycle. At each zero detection an interrupt can be generated. At each zero detection a waveform can be transitioned. The waveform can be enabled onto the upper data bit.
IP-Parallel-IO Counter - Timer A Block Diagram
Counter / Timer B has a 32 bit up counter which can be cleared by the software. The counter output is masked with a user programmable value to select a particular counter bit or bits to use for interrupt creation. The counter output is also available to read via software and can serve as a real-time clock.
IP-Parallel-IO Counter - Timer B Block Diagram