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IP-Parallel-HV

24 HV Outputs and 24 HV inputs

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IP-Parallel-HV Description

  • Up to 50V IO
  • 24 outputs and 24 iputs
  • Built in reference for open collector IO. 6.5V standard. Adjustable.
  • External reference pin to allow for user reference voltage
  • FPGA controlled allowing for customized models
  • Industrial Temperature components standard
  • 1 year warranty standard. Extended warranty available.
  • ROHS and Standard processing available
IP-Parallel-HV Block Diagram Rev 5



Use IP-Parallel-HV to provide your higher than TTL IO needs. The base design provides a flexible user interface to control each signal. Interrupt generator on each input channel. filtered or direct input. The design is FPGA based [Spartan 6] optimized for client specific versions. Use IP-Parallel-HV for your control, avionics and robotics applications. Perfect for your embedded control applications. Supported with IP Carriers for PCI, PCIe, VPX, PCI-104, and cPCI . Interconnect with ribbon cables and breakouts or custom cables.

High Voltage IP Compatible card with 48 programmable IO. 200 mA sink. Low side switch configuration . Open collector interface. The IndustryPack compatible IP-Parallel-HV design can handle up to 50V external signals. The standard card configuration is a 6.5V reference plus the ability to supply an external reference. Other built-in voltages are available.

The 24 outputs can be synchronized to change with the same IP clock using the master enable. SW selectable.

The IP Module driver can control multiple cards by the same CPU. IP-Parallel-HV when coupled with the Dynamic Driver "knows" what slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right card.

PCI implementations can be done with the PCI3IP and PCI5IP. Applications from 24/24 to 120/120 HV IO per PCI slot.
PCIe implementations can be done with the PCIe3IP and PCIe5IP. Applications from 24/24 to 120/120 HV IO per PCIe slot.
cPCI 3U is supported with the cPCI2IP. Applications with 24/24 or 48/48 HV IO per 3U cPCI slot.
cPCI 6U is supported with the cPCI4IP. Applications from 24/24 to 96/96 HV IO per 6U cPCI slot.
Applications from 24/24 to 96/96 HV IO per PC104 stack position.
PC104p is supported with the PC104pIP. Applications with 24/24 HV IO per PC104 stack position.
PC104p situations with a custom mechanical can be done with the PC104p4IP.



IP-Parallel-HV IO Filter and Interrupt Control Block Diagram

IP-Parallel-HV Features

Size
1.8 x 3.9 inches nominal single slot IP Module. Type II with low profile devices on rear
IO
IP Module IO connector
Clocks
Compatible with 8 and 32 MHz IP bus operation. Oscillator position available
IP Decoding
ID, IO, Mem and INT spaces supported.
Parallel Interface
24 inputs and 24 outputs. Synchronization available for outputs. Open collector IO with programmable voltage reference - default is 6.5V, external voltage reference (diode coupled, up to 50V). Each IO can be an input or an output. Read-back filtered or direct.
Pull-up Resistor
3.6K ohm is standard. Alternate values can be utilized. .75W 1206 devices for pull-ups.
Synchronization
Outputs can be synchronized to change together [across register boundaries]. Synchronization can be disabled.
Protection
All IO are protected with current limiting resistors.
Interrupts
All IO can be programmed to cause interrupts. Each IO is programmable to be masked, active hi, active low, edge or level sensitive. Master enable for data channels. Status register with current interrupt request status. Interrupts are mapped to INTR0n on IP bus. Master enable can be disabled to allow polled operation.
Power Requirement
+5V, +12V.
SW Interface
All FPGA registers are read-write. All registers on word addresses.
Current Fab Number
10-2001-0305
Reliability
Belcore 25c GB 1.855 Million Hours (previous revision calculation, needs to be redone.
Custom
There is room in the FPGA for custom applications. Send in your specifications and we can quote a custom version for you

IP-Parallel-HV Benefits

Speed
The IP interface supports 32 MHz operation for quick data loading and unloading. The interface supports interrupts and polling. Dynamic Engineering carriers support 64 bit[PCIe models]/32 bit[PCI models] to 16 bit conversion in HW allowing for higher throughput and lower overhead.
Price
System level cost is best when reasonably priced reliable hardware is used and NRE minimized. With IP-Parallel-HV, driver support for the carrier and IP level, reference software, history of reliable operation, and fantastic client support your cost per unit and overall costs are attractive. IP-Parallel-HV is inexpensive and can save money in other ways too.
Ease of Use
IP-Parallel-HV is easy to use. A point and shoot user interface. Please download the manuals and see for yourself. The User Application software and driver will get you up and running quickly. SIngle and multiple card capable. The driver has direct calls to read or set any of the IO lines. The example software includes loop-back testing. Interrupts are supported with the driver, and tested with the reference software.
Availability
IP-Parallel-HV are stocked.
IP Specification Compatibility
IP-Parallel-HV is compliant per the VITA 4 - 1995 specification. Tested with PCI and PCIe based carriers. All Dynamic Engineering IP Modules are compatible with the PCIe3IP, PCIe5IP, VPXI2IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP etc. IP-Parallel-HV will operate with any IP specification compliant carrier board.

Part Number: IP-Parallel-HV
Ordering Options

  • IP-Parallel-HV Standard Model with open collector register based IO. Programmable interrupts, user settable open collector reference. Now combined with IP-Test.
  • -IP Crypto to interface with KYK-13 and similar interface. Read the key, provide to the host and remove data with approved method.
  • -HaveQuick Time Of Day receiver/transmitter using HaveQuick format data - manchester encoded with seconds, minutes, hours, days, year.
  • -Miller Add Miller encoded inputs and outputs to your system. See manuals tab for more information.

  • Add additional options to the "- number"
  • -ROHS Use ROHS processing. Standard processing is "leaded"
  • -CC Option to add Conformal Coating

IP-Parallel-HV Drivers

Software Support for IP-Parallel-HV includes: Windows® 10 and Linux compliant drivers
The IP driver is layered and operates on top of the Carrier driver. IP drivers are auto installed for each instance detected. Please see the Driver manuals for the specifics of each type.

Drivers and Reference SW are developed for each type / version of IP-Parallel-HV implemented. When custom versions are ordered the NRE will include providing Windows, and Linux. For off-the-shelf models, select on the manuals tab, the Windows® and Linux SW shown is included with your purchase of the HW. Unsupported SW versions may have an NRE requirement.

Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.

linux diagram
Reference diagam of how our Linux Driver / Application layer operate with the Carrier and IP Module.

IP-Parallel-HV Manuals

Click on the links to Download selected manuals in PDF format.

IP Carrier and Module Quick Start guide for Windows®10

IP-Parallel-HV and Test model HW Manual for revision 5 and later
IP-Parallel-HV and Test model Win10/11 Manual for revision 5 and later Use IP-Parallel-HV-TEST to develop a driver or test an IP Carrier. The Module responds to all 4 access types, allows testing of both interrupts, has 2K bytes of RAM and more to support your SW or HW development

IP-Parallel-HV-Miller Miller Interface version with 1RX and 1 TX port. Programmable interrupt options, 1Kx16 FIFO per port.
VxWorks IP Module Manual
IP Carrier Linux Manual
Linux IP Module Manual




Customer Special Versions