PC/104p-BiSerial-III
PCI-104, PC/104p, PC104+ Compatible
RS485, LVDS, ADC and DAC State-Machine IO
Full and Half Duplex Serial / Parallel Data Interface with DMA
Front View


Rear View



The PC/104p-BiSerial-III has been updated from the PC104p-BiSerial. Building on the knowledge and experience gathered from multiple IP, PMC, and PC/104p BiSerial implementations and adding in the latest technology has created the PC/104p-BiSerial-III. The BiSerial features large internal "BLOCK RAM" which can be used for FIFO or Dual Port RAM. The larger Spartan III® contains the PCI interface with DMA and the state-machines for your design. If deeper FIFOs are required; completely isolated FIFOs with 32 bit ports for increased adaptability and performance are available. 16 - 40 MHz 485 buffers with programmable termination and direction can be configured to your systems requirements. The expanded faster FPGA will implement the most complex state-machines. Many of the designs implemented for the PMC and IP versions can be ported to the PC/104p.

The Biserial family has been used for many applications including: telemetry, manchester encoding and decoding, command and control, interface simulation, "glue" between incompatible systems, radar systems, industrial interfaces, inventory, optical recognition, airborne, ground based, and ship based.

An example of a simulation application is the use of a BiSerial to simulate or emulate an expensive piece of equipment that is required for test. The BiSerial can be used to simulate a target system like an airplane, missile or other vehicle to interact with the equipment that would be connected to the target system. Many times having a computer based interface is more convenient than having the actual target application. Test, debugging, diagnostics etc. can be computer driven using the BiSerial much more easily than the "real" system in many cases. Consider the BiSerial family for your interfacing and support requirements.

Options include LVDS, DAC and ADC channels. There are 4 DAC, and 4 ADC channels which can be populated with 200 KHz. 16 bit devices. The analog and TTL IO can use the external FIFOs or the internal Block RAM when smaller FIFOs are needed.

Fully independent and highly programmable RS-485 / RS-422 / LVDS IO channels are provided by the PC/104p-BiSerial-III design. The channels are supported by independent state-machines created within the Xilinx FPGA. The channels can have the same or different protocols. Manchester encoding and decoding, standard serial [UART], control, command, instrumentation, and custom protocols can be implemented. For example the TG1 version has 4 receive and one transmit channels.

Typically each channel has a separate memory . The FIFOs are usually set to 32 bits wide to optimize data transfer from the PCI bus. The interface is optimized to minimize the latency on the PCI bus. The data transfer size can be anything on the IO side. The FIFOs support internal loop-back testing. The loop-back test can be used for BIT, and for software development. The programmable FIFO flags are supported on both sets of FIFO. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling. In addition to standard read-write access to the FIFOÕs the memory can ebe managed by DMA. Each channel has a separate controller allowing for true independent operation. The data files etc. can be set-up and managed with a minimum of interrupts with the larger file sizes allowed with a separated channel design. Scatter-gather and block mode DMA are supported.

The PC/104p-BiSerial has 16 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PC/104p-BiSerial. The RS-485 transceivers support up to 40 Mhz clock and data rates. When configured with LVDS IO the bandwidth increases toward 200 MHz. The actual top end will depend on the complexity of the design rather than the IO.

Eight TTL IO are provided for flexibility, and to remove the need for an additional card when only a few bits are needed. The state-machines can be coupled to the TTL IO or they can be used as a separate parallel port or other function.

The base design has a PLL, oscillator position, and PCI clocks to choose from for a variety of clocking options. Custom oscillator frequencies can be installed when an exact frequency is required. The PLL can be used to create custom frequencies. The PLL is programmable via I2C bus. The driver supports programming the PLL.

If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

PC/104p-BiSerial Block Diagram



The "standard timing" options are toward the bottom of this page. Sometimes the versions we already have developed are perfect for our customers requirements. Othertimes our customers need something that is "just like but different". Please let us know what you need and we can implement it for you.




PC/104p-BiSerial-III Features

  • Size
    		•  Standard PCI-104 or PC/104p

  • IO Speeds
    		•  40 MHz RS485 signaling supported. LVDS transceivers rated at 200 MHz. Xilinx may limit the top rate, 200 KHz ADC, 200 KHz DAC, TTL is Xilinx driven.


  • Clocks
    		•  PLL [Cypress 22393], PCI, OSC, External clock sources are available for use

  • PCI
    		•  Standard 33 MHz. operation. Standard 32 bit operation. Independent DMA support for each TX and RX channel available

  • Software Interface
    		•  Registers are read-writeable. Transmit and Receive functions separated.

  • Interrupts
    		•  Transmit and Receive state-machines, FIFO Programmable almost empty [transmit] and programmable almost full [receive] have programmable interrupts. Status can be polled for non-interrupt driven operation as well.

  • Signaling
    		•  16 RS-485 / RS-422 compatible IO are provided. Any combination of transmit or receive channels can be created. Programmable termination. LVDS IO are available on all channels. Up to 4 DAC channels and/or 4 ADC channels can be added. Each channel can operate at 200 KHz and has a 16 bit resolution. 8 TTL IO are provided.

  • IO
    		•  The IO is available via the 50 pin right angle header. The differential IO is properly routed with controlled spacing and matched lengths on each of the pairs. Custom cables are available.

  • Interface
    		•  Custom programmed interfaces are available, standard options are shown below.

  • Power
    		•  +5, 3.3, 2.5, 1.2. 3.3, 2.5 and 1.2 converted with on-board regulators.

  • Memory
    		•  Separate external FIFOs are options.
    4K, 8K, 16K, 32K, 64K, and 128K x 32 are available. Internal FIFOs or Dual Port RAM are standard. Ex. 16 - 1Kx32 internal FIFOs




    PC/104p BiSerial III Benefits

  • Speed
    		•  The PCI-104 / PC104p BiSerial III is optimized for interfacing requirements. The FIFO memories, DMA, and programmable interrupts off-load the CPU from most of the management other implementations require. The FIFO access is optimized for the PCI bus and can be performed with DMA reducing overhead and speeding up the data transfer. Each channel has its own DMA controller allowing for multiple independent data streams from a single card. Large and small data transfers can be managed with minimal overhead required. On the IO side the PMC BiSerial III has independent channel functions. Channels can operate at maximum rate in parallel.

  • Price
    		•  The PCI-104 / PC104p BiSerial III is easily programmed to implement new functions. Many previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. a modified BiSerial III will represent a large cost savings in your budget.

  • Ease of Use
    		•  The PCI-104 / PC104p BiSerial III is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and engineering kits help with integration into your system. We can write a custom Windows® or Linux driver for you.

  • Availability
    		•  Dynamic Engineering works to keep the PCI-104 / PC104p BiSerial III in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with a standard version then send updated programming files later to help get your project going - right away.

  • Size
    		•  The PCI-104 / PC104p-BiSerial-III is a standard single width PCI-104 / PC104p card, and meets the PCI-104 and PC104p mechanical specifications. The PC/104p-BiSerial-III can be used in all PC/104p and PCI-104 slots.

  • PCI-104 PC/104p Compatibility
    		•  The PC/104p-BiSerial-III is PC/104p and PCI-104 compliant per the PC/104p and PCI-104 specifications.

  • PCI Compatibility
    		•  The PC/104p-BiSerial-III is PCI compliant. You can develop with a PCI to PC104p adapter - PCI2PC104p


    Ordering Information
    Cards come without ISA connectors unless requested
    Please select board option and Engineering Kit

    Quantity
    1 year warranty
    Quantity discounts available


    Engineering Kits
    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    PC104p-BiSerial-III-Eng-1 .......... Hardware Support Engineering Kit includes:
    Board level Schematics [PDF], PCI2PC104p, HDRterm50, HDRribn50

    PC104p-BiSerial-III-Eng-2 .......... Hardware Support plus Driver Engineering Kit includes:
    Board level Schematics [PDF], Software[PC104p-BiSerial-III Driver and sample application zip file ], PCI2PC104p, HDRterm50, HDRribn50-3.

    PC104p-BiSerial-III Drivers .......... Software Support Only Windows®XP and 2000 compliant drivers for the PC104p-BiSerial-III:


    PC104p_BiSerial_III Options Summary
    PC/104p-BiSerial-III-custom - custom versions with customer specified state-machines, Xilinx, and FIFOs.
    If your design needs less memory the internal XIlinx FIFOs can be used saving you money.
    PC/104p-BiSerial-III-TG1 - See definition below
    PC/104p-BiSerial-III-BA14 - See definition below
    PC/104p-BiSerial-III-DDL - See definition below
    PC/104p-BiSerial-III-NVY5 - See definition below
    PC/104p-BiSerial-III-NVY6 - See definition below


     Manuals
    Customer Special Versions
    You can order these too, or send us your request and weÕll design one for you

    "TG1" The PC104p-Biserial-III-TG1 has been implemented with 4 receive and one transmit Instrumentation channels. Each channel is supported with a separate DMA engine. The main function is to receive data from four sensors on a continuous basis. The DMA enables a low power processor to be used to manage the data flow with the TG1 doing most of the work. The interface uses a three wire interface with data, clock and strobe. Each channel is independent with respect to the reference clock and strobe.
    Please download     the TG1 Hardware manual or the TG1 Windows® Driver Manual in PDF for more information


    "BA14" PC104p-Biserial-III-BA14 has been implemented with one receive and one transmit channel. Each channel is supported with a separate DMA engine. One of 8 possible inputs can be selected. 8 copies of the transmitted signal are supplied. The main function is to transfer data with specialized "RCB" or "WRA" equipment. The controlling drawing was originally from Litton. The interface uses a UART like protocol with marking state, start and stop bits, 16 bit data plus cmd/data bit. MSB first. The programmed frequency is 6.25 MHz.

    BA14 Hardware manual
    BA14 Win32 (XP) Driver Manual
    BA14 Win7 Driver Manual


    "DDL" Dynamic Data Link. The PC104p-Biserial-III-DDL protocol implemented provides two programmable channels each operating in either master or slave mode. Each channel is supported with a separate DMA engine. Clock A from the PLL is used as an eight times clock reference for the DDL serial interfaces which transfer data at the rate of 100 k bits/second. Six differential I/O are used for the I/O signals. The DDL interface sends and receives 17-bit words (16 bits of data plus one parity bit). LSB first along with an active high enable signal and a gated clock. The data changes on the rising edge of the clock and is stable on the falling edge. The enable signal is asserted one bit period before the rising edge of the first clock and is de-asserted one bit period after the rising edge of the last clock. There is a programmable delay between data words that can be set to from 1 to 255 bit periods. A parity bit is always appended to a data-word and can be set to use either odd or even parity. For detailed information please refer to the hardware manual.



    "NVY5" PC104p-Biserial-III-NVY5 has been implemented with one 16 bit transmit channel. NVY5 accepts system data or uses DMA to fill the local memory. 16Kx16 TX memory. When a programmed level is achieved, a programmable width pulse is generated [DataReady]. External HW supplies a reference IO clock and ReadEn. ReadEn is asserted for the duration of the data transfer. Frequency is cable dependent. For short cables 20 MHz. Longer cables can be used at lower frequencies.
    Please download NVY5 Hardware manual in PDF for more information


    "NVY6" PC104p-Biserial-III-NVY6 has been implemented to serve as a test bench for the NVY5. PLL based external clock rate, provides clock and REN to NVY5, accepts 16 bit data and DataReady. 16Kx16 receive memory with DMA support.
    Please download NVY6 Manual TBD. Very similar except reverse process for NVY5.


    Related Products
    HDRribn50 50 pin Ribbon Cable
    HDRterm50 Ribbon Cable 50 pin terminal block adapter
    PCI2PC/104p PCI to PC/104p adapter card
    PCIBPC/104p Bridged PCI to PC/104p adapter card to allow full PCI-104 stack to be implemented in a single PCI slot.
    PC104p Chassis with multiple length options, rugged, conduction or convection cooled
    PC104p 12 V Power Supply converts 12V reference to 5, 3.3, -12, and -5
    PC104p 28V Power Supply converts 14-34 reference to 5, 3.3, -12, and -5


    Cable for "TG1" custom cables are available for your project.

    Custom, IP, PMC, XMC, PCIe, PCI, VPX, VME Hardware, Software designed to your requirements



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