ccXMC-Serial

ccXMC-Serial [conduction cooled XMC model "Serial"] is a new design inspired by PMC-Serial design. The PMC version was based on Z85230 and external UARTs. ccXMC-Serial is an upgrade with the communications processing happening inside the FPGA allowing for greater speed and flexibility. The initial [default] design incorporates 2 HDLC ports, 2 NRZ ports and 3 UART ports. The UART ports make use of the programmable RS-232/RS-422 IO to provide user selectable operation. RTS/CTS are supported. The UART is implemented with the Dynamic Engineering standard UART design which can operate in the traditional 8 bit per word mode as well as 32 bit, packetized [mixed] provide programmable gaps between transfers and more. The NRZ ports are highly programmable. The HDLC ports take care of the formatting, zero stuffing and removal, CRC calculation and checking. Future models will have additional / alternate port definitions.

The IO can be configured to support one function, one function replicated several times, or multiple functions. A real space saver when you need to have some Manchester to go with your UART and HDLC ports. A partial list of functions implemented in "Channels" includes: NRZL, Manchester, Miller, SDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive. To support the functions the designs include: memory elements instantiated with FIFO, Dual Port RAM, DDR, register files, as well as state-machines, counters, timers, dividers, registers, CRC and Parity generation / checking, software drivers and applications, DMA [direct memory access] and the glue that goes with it. Our designs are written in VHDL and done in a heirarchy allowing direct porting of different features to create new implementations.

The original design was used on P-3 and other platforms. Where can you use the new ccXMC-Serial?

A new custom version can be implemented in a very reasonable time. Typically a few weeks of design time for a medium sized project including the new VHDL set, Windows® or Linux driver, reference software package, and documentation. Examples of the designs performed to date are listed toward the bottom of this page and pages for other versions of other FPGA based designs including our BiSerial line. Designs listed on this page are NRE free as they are implemented. Designs requiring porting may require NRE to implement.

We can be rapid with our response because the designs are structured to allow ports to be moved in and out to create new design sets. Most designs have a fairly large component of reused "known good" VHDL we can pull from allowing focus on the new functions required for your implementation. You are getting the benefit of many man-years of design and test time with each new version created. For example, in the base HDLC implementation the UART came from our BiSerial family, The NRZ from the ORN1 project on ccPMC-BiSerial-VI, and the HDLC was an update to our SDLC design also from the ORN1 implementation. Join our high reliability clients taking advantage of Dynamic Engineering know-how to help speed your project to completion.

ccXMC-Serial can be used along with a PCIe or other carrier/adapter to use with a variety of system types - PCI, PCIe, PC104p, VPX cPCIe, etc.. Dynamic Engineering has XMC carriers for PCIe, cPCIe, and can do custom design to specific client requirements as well. Please use the pull-down menu to navigate to other Dynamic Engineering products including carriers.

XMCs are independently specified through VITA for the form factor, connectors and pinouts of the PCIe signaling; you can use ccXMC-Serial design with any carrier from any vendor that supports standard XMCs. To support integration into a variety of systems, ccXMC-Serial can operate with VPWR set to 5V or 12V, and an inter-spacing gap of 10 or 12mm. The carrier side connector will need to match the inter-board gap desired.

It all starts with the PCB [Printed Circuit Board]. Quality design and quality materials are required to meet the strenuous requirements of many of our implementations. You can do the job quickly or you can do the design correctly. We pride ourselves on taking the time to put the extra work into our layouts. The quality goes in before the parts go on. In addition to routing strategy and layer counts, Via size, plating requirements, break-out trace widths, and materials are areas where quality comes into play. The via size and method of trace attachment to the via affect the signal shape and reliability. Using tear-drop trace connections to pads, vias and through hole components enhance the reliability and minimize the impedance discontinuity resulting in a cleaner signal. Using larger vias provides adequate copper for proper power distribution and more surface area to bond to where traces are interconnected. The combination provides better vibration endurance than smaller vias and traces would provide. The design has several power planes with sufficient copper weight and coverage to provide the references required for the routing plus the current and voltages needed by the various devices on the board.

ccXMC-Serial is compliant with the PCIe, XMC, and conduction cooled addendum specifications. One of the features of our implentation is holding tighter tolerances than required by specification. This approach provides extra margin and allows better operation with other hardware since the error budget is essentially increased for the other portions of the sytem.

The IO section has requirements based on the IO type and the purpose for the IO. A very conservative approach has been taken to allow operation with any client requirement. The IO has two sections. The first 16 transceivers and can be LVDS or RS-485. The remainder are programmable RS232/RS422. The IO on the connector side is differential with a 100 ohm impedance requirement. Between the FPGA and the tranceivers the IO is single ended. Each IO has separate direction, termination, and data lines to allow complete flexibilty. The design has matched length connections from the FPGA ball to the seating plane of the connector. The lengths are matched to the "mil". The Impedance is controlled and the signals routed with proper spacing to avoid cross talk etc. The other features including memory, PLL, oscillator, and power supplies are implemented within the PCB to exceed the operational requirements for those devices.

The Spartan VI has internal block RAM which can be configured in a variety of ways. Currently, up to 268 BRAMs can be configured for internal channel memory support. In addition the memory can be configured as Dual Port RAM to allow direct addressing and retransmission of repeated patterns.

Sometimes you just need more memory. DDR is available with 256 Mbytes. The DDR is supported with FPGA based FIFOs and a controller to allow more than one port to use the memory. Internal loop-back is supported. The loop-back test can be used for BIT and for software development. Programmable FIFO flags are supported on both sets of FIFOs. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any depth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling. In addition DMA can be programmed to fill or empty the FIFO with sizes larger than the FIFO size. The DMA is hardware controlled to be held off when no data is available or no room is available. A new feature added with the DDR implementation is programmable boundaries to the memory. Software can set the amount allocated to each function supported by the DDR. With the "Channelized DMA"™ capability and large FIFOs the software application can have reduced interrupt counts to deal with while supporting larger and faster IO transfer rates.

ccXMC-Serial has transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO with ccXMC-Serial. Both RS-485, LVDS, RS-232 are supported. The RS-485 and LVDS are 3.3V devices allowing mixed operation if desired. RS-485 transceivers support up to 50 MHz rates. The LVDS transceivers are rated at better than 200 MHz. RS-232 covers the standard baud rates.

The IO is available through Pn6 - See other models if your system needs bezel IO. The lower RS-485/LVDS IO are protected with transorbs for over-voltage situations.

Clock options are frequently a major factor in embedded designs. Getting the right reference to the right part of the design and allowing for local control of exact frequencies. ccXMC-Serial has a PLL with 4 programmable outputs, reference oscillator, internal DCMs and buffering plus programable dividers instantiated within the VHDL. The PLL can be programmed to "any" fixed frequency, the DCM used to create phase variations, and local dividers to allow on-the-fly channel based frequency changes. In addition, 16 signals are looped back local to the FPGA to allow derived clocks to be used as clocks with the Spartan 6 architecture.

"Channelized DMA"™ is an important feature of the ccXMC-Serial design. With "Channelized DMA"™ you have a separate DMA engine for each transmitter and each receiver within each channel. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency. In systems where DMA is not warranted psuedo DMA can be implemented with the driver moving arrarys to / from the HW at high speed.

If your situation demands a custom application we will update the Xilinx FPGA and IO components. Send us your timing and we will send you the interface. Please refer to the bottom of this page for previously completed "customerized" ccXMC-Serial implementations.
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XMC-Serial Block Diagram
XMC Modules require a "carrier" in most cases to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats.
PCIe implementations can be done with the PCIe8LMCX1 and PCIe8LXMCX2
cPCI 3U is supported with the cPCIBXMC3U32
VPX 3U is supported with the VPX8LXMC3U