IP-CAN

Shown with Isolation - Power supply and signals

Now you can "talk" to your car and other CAN compatible network devices using IP-CAN. Two channels with Isolation or direct coupled, on board termination or cable based, 8 or 32 MHz IP operation, up to 1 MHz CAN bus operation, and an industry standard CAN bus controller. IP-CAN is currently supported with the Dynamic Engineering Carrier software drivers for Linux and Windows®. Use an existing IP slot within your chassis or combine with a carrier to make PCI-CAN, PCIe-CAN, PC104p-CAN, VPX-CAN or cPCI-CAN.

The IP Module driver can be instantiated multiple times to control multiple cards by the same CPU. IP-CAN when coupled with the Dynamic Driver "knows" what slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI/PCIe system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right device.

IP-CAN is an IndustryPack Module with two channels of CAN - Controller Area Network. Each CAN channel incorporates the SJA1000 and SJA1041 to provide BasiCAN and PeliCAN operation. Each channel is independent and can be programmed to run at different rates etc. The design utilizes a Xilinx FPGA to provide the IP interface - IDPROM, Bus interface, registers, and control for the CAN controllers [SJA1000]. The CAN interface is done in the memory space using an address bit to distinguish between the two channels. Standard word based offsets are used to memory map the CAN interface into the IP space.

The buses between each of the CAN controllers and FPGA are independent. Completely independent operation the result. The CAN controller is referenced to a 24 MHz. clock. The clock is driven from the FPGA to allow the FPGA to use a rate doubled clock for internal timing synchronization. The conversion from IP to CAN and vice-versa is done with a minimum of delay using the higher reference clock. The number of wait-states utilized is programable based on the IP reference clock. 8 and 32 MHz operation are supported. For maximum efficiency the 32 MHz rate is recommended. All Dynamic Engineering carriers are programmable on a slot-by-slot basis for 8 and 32 MHz operation.



IP-CAN is interconnected to your system with direct or isolated coupling. In the direct mode the CANL and CANH signals are routed to the IP IO connector "directly". A parallel split termination is provided with either the programmed 60.4 ohms per side or 1K ohms per side. With the revision 2 cards, the termination is programmable with software. Select the 1K termination for systems with terminations provided in the cabling or on another board. For home-run wiring or if IP-CAN is the last device the 60.4 ohm termination is recommended.

Isolated connections are accomplished by the use of a separate isolated power supply to provide power to the transceivers [SJA1041] and galvanic coupling on the signals between the transceiver and controller or FPGA. The power supply uses a split transformer to provide independent isolated power for each channel as well as between the board and the system.

The software interface is designed to be consistent and straight-forward. The IP interface provides the board level control with a base register and one channel control register per channel. The transceiver mode, master reset, and interrupt masking are accomplished in the channel control registers. The status register provides the channel interrupt and error status. The base level registers are located in the IO space. The base register provides the IP clock selection [8 or 32 MHz timing] and a software interrupt. The CAN registers are located in the IP Memory space to allow a direct decoding with the standard SJA address definitions. The hardware manual has a complete register map and bit maps for the FPGA registers.


There is ample room within the FPGA to add custom state-machines etc. as your needs require. Please contact Dynamic Engineering with any special requirements.

PCIe implementations can be done with the PCIe3IP and PCIe5IP. Applications from 1 to 10 CAN connections per PCIe slot.
PCI implementations can be done with the PCI3IP and PCI5IP. Applications from 1 to 10 CAN connections per PCI slot.
cPCI 3U is supported with the cPCI2IP. Applications from 1 CAN connection to 4 per 3U cPCI slot.
cPCI 6U is supported with the cPCI4IP. Applications from 1 CAN connection to 8 per 6U cPCI slot.
PC104p is supported with the PC104pIP. Applications with 1 or 2 CAN connections per PC104 stack position.
PC104p situations with a custom mechanical can be done with the PC104p4IP.
Channel counts from 1 CAN connections to 8 per PC104 stack position.
3U VPX is supported with the VPX2IP. Applications from 1 CAN connection to 4 per 3U VPX slot.
6U VPX is supported with the VPX4IP. Applications from 1 CAN connection to 8 per 6U VPX slot.