PCIe8LXMCX2HL

Embedded applications frequently require real time processing coupled with special purpose IO. With PCIe8LXMCX2HL´s two positions a PrXMC can be matched with another XMC to make a high bandwidth processing node. The PrXMC can communicate with the host for set-up, and then use the switch to interconnect with the special purpose IO card. With a local processing node of this nature you can use many in parallel with only one computer to provide the system management. For example - 10 in an expansion chassis without overloading the buses or management system.

A powerful PCIe 32 lane switch is at the center of the PCIe8LXMCX2HL design. The switch has many capabilities including operating from 1-8 lanes, operating at Gen 1, Gen 2 or Gen3 or mixed IO rates, supports lane reversal and polarity inversion. Support for max payload size transfers up to 2048 bytes ea., fully compliant with the PCIe base specification. The switch has 8 PCIe lanes connected to the PCIe "gold fingers" and 8 to each of the XMCs. The PCIe reference clock is buffered with a Gen1/Gen2/Gen3 compatible clock buffer. The clock buffer is specifically designed to handle spread spectrum and rate locked clocking operation. The buffered clocks are routed to the switch and the two XMC positions. A local power supply and heavy filtering insure stable power and reliable operation for the switch. The PCIe lanes to/from the switch are routed per PCIe specifications with matched lengths and impedance control.

PCIe8LXMCX2HL (PCIexpress Bridge PMC 2 slots HOTLink Rear IO) adapter / carrier converter card provides the ability to install two XMC cards into a standard PCIe slot. Slots with 8 or more lanes are compatible - 8, or 16 for example. PCIe8LXMCX2HL has two XMC card positions. XMC operation with 2.5/5/8 Gbps. PCIe8LXMCX2HL can act as a transparent switch or be programmed to allow private operations on the back side [PCIe] bus.

XMC user IO connector Jn4 from both positions is routed to a 20 position right angle SMT connector with 8 differential pairs. In addition single ended signals are brought to 3 headers to support secondary bus signals - strobes, time, or other control. The XMC front panel connector for slot 1 is mounted though the PCIe mounting bracket.

For superior performance PCIe8LXMCX2HL has two cooling cutouts per position for increased airflow to the XMCs. If your application requires a fan you can order PCIe8LXMCX2HL-FAN( ) to have fans mounted to your PCIe8LXMCX2HL. FAN positions are numbered 1-4, position 1 is closest to the PCIe Bezel [left edge in the picture above.] One fan can be mounted per position. Fans can be mounted to blow onto the XMC or to pull air from the XMC (R option.)

The -12V, 5V, and 3.3V for the XMC are regulated on board. The power supply designs utilize switching regulators controlling a MOSFET to convert 12V. An LC filter ensures clean power at the XMC. The Switch/Clock Buffer uses a small amount of 3.3V plus .9V and 1.8V derived from +12. The PCIe gold fingers are rated for 1.1A each, and a total of 5.5A on the +12V rail. 55W are available to the XMCs after power conversion. Please note this is the combined power requirement across the +12, -12, +5, and 3.3V power used by the XMCs. In most cases 55W is sufficient. PCIe8LXMCX2HL includes has a cable connector to allow additional 12V power to be added to the card. The two 12V supplies are DIODE coupled. In some cases the 12V supply on the backplane will not be adequately routed by the PC causing voltage sag on the 12V. If this occurs use the cable connector to compensate. Standard 2x3 PC connector.

The power supplies include the bulk capacitance to properly bypass the FETs and post conversion voltage rails. In addition the XMC connectors are bypassed with a .1 uF capacitor at each power pin. The power supplies are checked with voltage monitor circuits. The LEDs are not illuminated unless the voltage is within the defined range. Two headers allow user selection of 5V and 3.3V power on characteristics. The user can select [with shunts] Instant On, Delayed On, and disabled. If your design does not use one of the rails you can turn it off. If your system enumerates early in the power up cycle you can select instant on. If your system can use the delayed load on the power supply to advantage select delayed. 5V and 3.V supplies are rated 15A.

The XMC specification calls out "VPWR " which can be either 12V or 5V. PCIe8LXMCX2HL has FET switching and a header to allow user selection of either 12V or 5V or neither voltage to be supplied to these 8 pins [per XMC]. The selection is separate per XMC position. Build options are provided to allow "pre selected" voltages on these pins without the headers. The 12V asnd 5V supplied are part of the same power budget mentioned above. It is suggested the user select the rail definition most efficient for use, alternatively based on noise, the 5V will likely be quieter since it is converted on board and isolated from the 3.3V rail.

The signals routed from pins on the Jn4 (PN4) connector for each position are routed with matched length, impedance controlled differential traces suitable for single ended and differential operation.

The XMC JTAG connections for position 0 and position1 are routed to separate headers centrally located between the XMC devices. Please let us know if you want this header installed. [-JTAG12]

The PCIe bus does not have a concept of global addressing. A DIPSWITCH is provided to allow the user to select the Global Address on both XMC positions individually.