IP-Parallel-HV Have Quick
IP Compatible Time Code Data ------- Manchester Encoded Serial Data Interface
The IP-HaveQuick [IP-Parallel-HV-HQT] is part of the IndustryPack® Module family of modular I/O components by Dynamic Engineering. The IP-Parallel-HV is capable of providing high voltage interfaces with programmable state-machines. 24 Inputs and 24 outputs make serial and parallel interfaces possible. The HaveQuick protocol implemented provides a target and a master capability with software selection.
The target will wait for the 1 PPS pulse then synchronize with the manchester encoded data. The data carries the time code. Once synchronized and the data validated the decoded data is stored for reading by the host computer. There are programmable interrupts which can be used to alert your software to the new time code being available. The data is locally extended to provide the time between the received time. The time code provides very accurate time to the second. The hardware interpolates and provides higher resolution time which is re-synchronized with each 1PPS pulse received. Please contact Dynamic Engineering for this design or a custom modification to meet your requirements.
IP-HaveQuick Block Diagram
In Master mode the 1PPS signal, data and discrete are output from the IP-HaveQuick. The data in master mode comes from a counter which has presettable fields. The software can preset the year, day, hour, minute, second, and quality factor. The software will start by setting the transmit bit. The counter will progress and output the 1PPS once per second followed by the manchester encoded time code. The counter has a resolution down to the microsecond allowing the local host better resolution to the current time. The outputs can be masked in the case where the local host uses the IP-HaveQuick as a target and needs another local timer.
The modes [Master and Target] are independent to allow both to be active for loop-back testing.
All configuration registers support read and write operations for maximum software convenience, and all addresses are long word aligned.
The IP-Parallel-HV conforms to the VITA IP standard. This guarantees compatibility with multiple IP Carrier boards. Because the IP may be mounted on different form factors, while maintaining plug and software compatibility, system prototyping may be done on one IP Carrier board, with final system implementation on a different one.
Various interrupts are supported by the IP-HaveQuick. Each interrupt is individually maskable. Interrupt conditions are held until explicitly cleared via software.
Further information including timing diagrams, register bit maps and descriptions, connector pinouts etc. are included in the hardware description manual. Please download the manual for your reference.
IP-HaveQuick Timing Diagram
If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface....
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Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design.
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