• Windows® or Linux driver included with purchase
  • 32/33 Universal Voltage PCI operation ↣ can be installed in any PCI slot.
  • 5 IndustryPack Module positions w/ 8⇆32 MHz. operation
  • Fused, FIltered 5V, +12V, -12V supplied to IP´s
  • 32 bit access handling to IP´s
  • Full memory space supplied to each position
  • Full length PCI card
  • Ribbon Cable Bezel Cutout
  • High performance IO routing
  • 1 year warranty standard. Extended warranty available.
  • Extended Temperature standard.
  • ROHS and Standard processing available

5 position PCI IP Carrier, PCI IP Adapter, PCI IndustryPack® carrier, PCI IndustryPack® Adapter for IP modules

If you want to use IndustryPack® modules with your PCI system then PCI5IP is the choice for you. PCI5IP combines features you need with simplicity and speed. Up to 5 IP modules can be installed. 32 bit and double wide modules fit right in. Each slot has independent operation - control, clocking, IO, power filtering and protection. The PCI5IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result the PCI5IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows 7, Windows®XP/2000 or Linux drivers operation can be "plug and play". PCI5IP is a mature design recently updated to revision G on the PCB. Thousands shipped and still in operation. Dynamic Engineering launched PCI5IP in 2002 and still supports today. Industrial Temperature components standard. Our base drivers are written to support both PCIe and PCI based IP carrriers allowing our IP drivers to be common for both bus types. This means an IP driver developed for PCI5IP will work with PCI3IP, PCIe3IP, PCIe5IP, cPCI2IP, cPCI4IP, VPX2IP, PCI104-IP etc. For newer platforms requiring PCIe please consider PCIe3IP and PCIe5IP designs.

Our customers are our best source of feed-back and new ideas to implement. A new addition to the design of the PCI5IP is to tag all accesses from the PCI bus. IP Modules can take longer than the PCI response specification leading to the use of retry cycles on the PCI bus. In a single CPU system the retry accesses are done serially. The current IP access will be the correct one to respond to the retry access. In a multi-CPU system it is possible to get out of sequence accesses, and potentially have the IP response sent to the wrong retry access. By storing the PCI parameters for the IP access and only responding to the correct retry cycle; multiprocessor cross contamination is avoided. With revision G fabs PCI5IP has FLASH instead of PROM´s for better manufacturabilty, reliability and field support.

Multi-board operation is supported. With multiple PCI5IP´s in your system and unique cabling, sensors etc. for each slot on each PCI5IP it is important to "know" which PCI5IP is which and to properly control the IP modules mounted to them. A surface mount "dip switch" is provided to create a programmable identifier to the software. A specific PCI5IP can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus. The Dynamic Drivers make use of the Switch and Slot information to uniquely identify each installed IP and to associate a system "handle" with a particular module.

Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together for the five slots plus the state-machine. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation across the 5 IP´s and the controlling state-machine. A well designed clock distribution is critical for reliable operation.

Each slot has resettable "self healing" fused filtered power. +5,+12, and -12V supported.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. The connector are "wired" 1:1 from the IP IO connector to the Header connector. The Headers are numbered with standard ribbon cable conventions. The traces are matched length between the IO connector and header for each channel. The fist IP position has options for Right angle through the bezel and vertical connectors. Vertical connectors are provided in the remaining positions. Ribbon cable or discrete wire cables can be interfaced directly with the PCI5IP. Alternatively the HDRterm50 can be used to create a terminal block interface. The right angle connector in position A comes with ejectors, and an ordering option for ejectors for the remaining positions is available. This is not the default option due to PCI height restrictions. A recomended upgrade if your system has the room. "-EJ" The front panel can be supplied with a blank bezel or the ribbon cutout version. Please order "-BB" for the blank option. The ribbon cutout versions is required for the right angle connector configuration. A full list of ordering options are available toward the end of this Dynamic Data Sheet.

Slots B/C and D/E are configured to accept two single IPs, or a double wide Industrypack compatible design. Slot A is available for single IP´s. The data bus is designed to allow for 32 bit IP Bus operation. The data bus width is controlled by the address range the slot is controlled with. Automatic switching makes it possible to switch data bus size without changing the control registers for seamless operation.

Three methods of resetting the IP´s are built into the PCI5IP. A local pushbutton reset switch is provided. The switch is accessible between slots C and D. The IP´s can be reset from the control register within the FPGA via the software interface. The IP´s are reset on power-up via a supervisory circuit that guarantees the 200 mS minimum reset requirement in the IP specification. The resets only affects the IP slots.

LED´s are provided to each of the five IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s [3] are provided on slot C. An additional eight user LED´s are available for debugging or other purposes.

IndustryPacks are usually 16 bit devices and the PCI bus supports 32 bits. PCI5IP accepts 32 bit PCI accesses and converts them into two 16 bit accesses with an auto-incremented or static address. One PCI access can be used to write to or read from two IP locations or twice to one location. Byte, Word and Long Word accesses are supported to the 16 and 32 bit IP sites from the PCI bus. If a 32 bit IP has been installed then direct 32 bit operation can be utilized.

The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the PCI5IP is created. The PCI5IP responds normally to the host, not tying up the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences. Multi-threaded software operation is supported with separate bus error status in each of the slot control registers.

The PCI bus is defined as little endian and many IP´s have their register sets defined to operate efficiently with a little endian interface. The default settings on the PCI5IP are "straight through" byte for byte and D15-0 written to address 0x00 before D31-D16 written to address 0x02 when long words are written to 16 bit ports. Please note that any long word address can be used. The lower data is written to the lower address first, then the upper data to the upper address. Each slot has a ByteSwap and WordSwap control bit to allow Byte and Word Swapping to be performed to accommodate alternate IP and OS requirements.

Byte Swapping accesses to a 16 bit port.

Byte Swapping access to a 32 bit port

With Rev G and later boards the IO routing from each IP module IO connector to the associated box header is done with matched length, impedance controlled, differential traces. 1-2,3-4,..23-24, 25-50, 26-27 48-49. With this pattern the differential pairs can be properly routed for both the IP and Header connectors with adjacent pin pairs used except for the single 25-50 pair. Frequently 25 and 50 are grounds. Routing is still 1:1 as well making signal tracing through the carrier easier to deal with.

Connector positioning is compatible with IP-Debug-Bus to allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the PCI5IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

PCI5IP Features

  • Size
  • Full size PCI card.

  • IP compatible slots
  • 5 independent slots. Slots B/C and/or D/E can be used together for a double wide or 32 bit IP

  • Clocks
  • Each slot has independent selection of 8 and 32 MHz operation. State-machine auto-synchronizes to each access.

  • Access Width
  • Each IP Module can be accessed as byte, word, or long word. Long words are converted to double word accesses for 16 bit slots.

  • Bus Error
  • The Watch-Dog timer protects against PCI bus hangs by responding when the IP is not installed or has a failure. 7.3 uS timeout.

  • Cable interface
  • Industry standard 50 pin box header connectors. Vertical mount [B-E] and either right angle or vertical position A.

  • Software Interface
  • Control registers are read-writeable
    IO, ID, MEM, INT spaces supported. Windows 7, Windows XP, VxWorks, and Linux drivers available.

  • Interrupts
  • Each IP has 2 potential interrupts. All 10 are routed to INTA on the PCI bus. Control registers are provided to determine the source of the interrupt

  • Power Requirement
  • +5V internally, +5V, +12V, -12V current determined by IP´s installed

  • LED´s
  • +5V, +12V, -12V and activity LED´s. 8 user LED´s also available.

  • DIP switch
  • An 8 position switch is available to support multi-board operation or other user defined purposes.

    PCI5IP Benefits

  • Speed
  • With the direct PCI to IP Bridge design featured in the PCI5IP standard accesses to your hardware happen faster than in competing designs. Throughput is increased by an additional 50% when the 32 bit access mode is used. Fantastic for loading memory etc. Now compatible with mult-processor systems without sacrificing access times for single CPU systems. Multiple threads with accesses to different IP´s are supported.

  • Price
  • System level cost is optimized when reasonably priced reliable hardware is used and NRE minimized. With the PCI5IP, driver support for the carrier and IP level, reference software, history of reliable operation, and fantastic client support your cost per unit and overall costs are attractive. Please check the current per item pricing with the storefront lower on this page. Orders can be placed via the on-line ordering system or via phone / email PO order systems.

  • Ease of Use
  • PCI5IP is easy to use. A point and shoot user interface to the IP sites. Please download the manuals and see for yourself. The engineering kit provides a good starting point for a new user. Reference software is provided in source form to get you started. The generic IP interface allows the driver to be used with IP´s without a driver specific to that design.

  • Availability
  • PCI5IP is still a popular board. We usually have PCI5IP in stock. With our in house manufacturing capability larger orders can be accomodated rapidly.

  • Size
  • PCI5IP is a full size PCI board which conforms to the PCI mechanical and electrical specifications. Eliminate mechanical interference issues. A metal card guide extension is supplied with PCI5IP.

  • IP Compatibility
  • PCI5IP is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with PCI5IP. All other IP Modules which are compliant with the VITA specification can be expected to work.

  • PCI Compatibility
  • PCI5IP is universal voltage, PCI compliant device. PCI5IP can be expected to work in any PCI compliant backplane. PCI5IP has been tested in multiple active and passive backplanes from Advantech, Dell, Intel, Apple Computer and other manufacturers. PCI5IP has been tested in expansion chassis by SBS. PCI5IP has been tested with industrial multi-processor systems .

    Ordering Information

    PCI5IP Standard 5IP carrier - Industrial temp with revision G. Right angle header connector at Bezel position with Ribbon Cable Bezel.
    -EJ Add Ejector Style Header connectors for the 4 non-bezel positions.
    -ROHS Use ROHS processing. Standard processing is "leaded"
    -BB Option to have a blank bezel without a cut-out. The Ribbon Cable Bezel is standard and includes a cutout to facilitate cable egress from the IP Modules. Note: -BB also causes bezel position to have a vertical box header connector.
    -VC Option to have vertical box header in bezel position while retaining the standard Ribbon Cable Bezel.
    -CC Option to add Conformal Coating

    To include a Driver with your order please select from below.


    Engineering Kits
    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    PCI5IP Drivers .......... Software Included with board order Win7, Win®XP & 2000 and Linux compliant drivers for the PCI5IP:
    PCI5IP-XP/2000 Win®XP & 2000 driver for PCI5IP. The driver is designed to be overlayed with individual IP Module(s) driver(s). Please see the Driver manual for the specifics of writing your board interface.
    Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design.

    Please select between the Linux and Windows drivers for your engineering kit, referring to the individual IP pages for driver availability. We are working on drivers for most of our IP´s and you can influence the order in which we complete them by letting us know which ones you need first! Please contact Dynamic Engineering if you would like us to produce a driver for your IP or a third party design.

    PCI5IP is a full length universal voltage signaling PCI card shown with 5 IP´s installed.

    Download the
    PCI5IP revision G1 Manual in PDF format.
    Download the IP Carrier Windows®7 manual. For PCIe and PCI based carriers
    Download the Win7 Generic IP Driver Manual in PDF format.
    Download the Carrier Group Linux Manual in PDF format.
    Download the Generic IP Driver for Linux Manual in PDF format.

    Use the Generic driver when a custom IP driver is not available. The generic driver is included with the drivers along with a sample user application making calls to the generic driver and an IP-Parallel-TTL.

    Please refer to the individual IP pages for driver availability. We are working on drivers for most of our IP´s. You can influence the order in which we complete them. Please let us know which one you need first.

    Related Products
    IP-DEBUG-IO II: IP IO Connector Break-out Adapter
    IP-DEBUG-BUS:IP module extender specialized for debugging
    HDRterm50 : 50 position terminal block with ribbon cable connector
    HDRribn50: Ribbon Cable for IP Modules with strain relief and cable pull tab
    IP-MTG-KIT: Mounting Hardware for IP Modules

    Custom, IP, PMC, XMC, PCI, PCIe, VME, VPX, PC104p, PCIe104 Hardware, Software designed to your requirements

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