cPCI2IP
cPCI2IP is a 3U 4HP cPCI [CompactPCI] design with 2 IP slots.





The cPCI [Compact PCI] compatible cPCI2IP design adds 2 Industrypack compatible slots to your cPCI host. The cPCI2IP acts as an adapter, converter, carrier, or bridge between the cPCI bus and your IndustryPack hardware. The cPCI2IP is a 3U 4HP cPCI design with 2 IP slots. Windows and Linux Drivers available.

Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together both slots plus the state-machine. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation across the IPs and the controlling state-machine. A well designed clock distribution is critical for reliable operation.

Each slot has resettable "self healing" fused filtered power. +5,+12, and -12V supported.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. The connectors are accessible via the bezel. Ribbon cable or discrete wire cables can be interfaced directly with the cPCI2IP. Alternatively the HDRterm50 can be used to create a terminal block interface. In addition the IP IO is routed to the J2 connector to allow backplane IO options. The J2 IO is an option which can be specified with the -J2 designation. cPCI J2 IO is in conflict with cPCI 64 bit PCI. Please be sure that your intended slot has 32 bit PCI bus and IO availability when selecting this option. Without the -J2 option the cPCI2IP will operate in 32 or 64 bit backplanes.

Slots A/B are configured to accept two single IPs, or a double wide Industrypack compatible design. The data bus is designed to allow for 32 bit IP Bus operation.

A local reset switch is provided for the IP boards. In addition the IPs can be reset from the control register within the Xilinx via the software interface. The reset only affects the IP slots. The PCI interface should only be reset via the backplane so that system addressing information is not lost.

LEDs are provided to each of the IP slots for activity indicators. When each slot is accessed the LED is flashed. The Xilinx provides a "one shot" circuit to stretch the "on" time to make it visable. Power indicator LEDs [3] are provided on slot B. An additional eight user LEDs are available for debugging or other purposes.

A surface mount "dip switch" is available for configuration control or debugging purposes. The switch values are available to be read via the PCI bus.

Most IndustryPacks are 16 bit devices and the cPCI bus supports 32 bit accesses with FAST technology. The cPCI2IP accepts 32 bit cPCI accesses and converts them into two 16 bit accesses with an auto-incremented or static address. One cPCI access can be used to write to or read from two IP locations or twice to one location. Byte, Word and Long Word accesses are supported to the IP sites from the cPCI bus.

IP Modules which support 32 bit accesses are supported with the combination of both slots A&B. The cPCI2IP automatically switches to 32 bit mode when the 32 bit access address range is used.
Byte and word lane switching are supported to provide a hardware solution when big vs little endian issues arise. Each slot has separate controls for maximum flexibility.

The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the cPCI2IP is created. The cPCI2IP responds normally to the host, not tying up the cPCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have undesirable consequences.

Connector positioning is compatible with IP-Debug-Bus to allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the cPCI2IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

Coming soon is the rear panel cPCI_IPIO break out which will act like a PIM Carrier specific to IndustryPack Modules. The 3U version will have 2 50 pin headers with 1:1 wiring from the J2 connector. The cPCI_IPIO will mount on the rear of the backplane and provide the equivalent of bezel IO on the rear. Please contact the factory for status on this project.

The IP IO connectors are available via the Bezel IO or the J2 backplane IO. Because of cPCI configuration issues three models of the cPCI2IP are available. -BIO, -J2 and Both. the -BIO is the default option. The bezel IO is accomplished with a stacked dual 50 pin header - 50 pin ribbon cable compatible. The J2 IO is isolated with 0 ohm resistors. When the -BIO option is selected the resistors are not installed to remove the added line length. If the cPCI backplane is configured for user IO instead of 64 bit cPCI then the J2 IO option can be used.

The cPCI2IP is a universal board design and can be used in any cPCI slot. The cPCI2IP is not keyed to allow installation into 3.3 or 5V cPCI defined slots.


cPCI2IP is a 3U 4HP cPCI [CompactPCI] design with 2 IP slots.


cPCI2IP Features
  • Size
    		•  3U - 4HP [single slot] PCI card.

  • IP compatible slots
    		•  2 independent slots. Slots A/B can be used together for a double wide or 32 bit IP modules.

  • Clocks
    		•  Each slot has independent selection of 8 and 32 MHz operation.

  • Access Width
    		•  Each IP Module slot can be accessed as byte, word, or long word. Long words are converted to double word accesses. 32 bit IP accesses to double wide slots.

  • Bus Error
    		•  The Watch-Dog timer protects against PCI bus hangs by responding when the IP is not installed or has a failure. 7.3 uS timeout. Separate status per slot.

  • Cable interface
    		•  Industry standard 50 pin header connectors. Bezel mount. J2 IO is also available.

  • Software Interface
    		•  Control registers are read-writeable
    IO, ID, MEM, INT spaces supported. Windows® and Linux drivers available.

  • Interrupts
    		•  Each IP has 2 potential interrupts. All are routed to INTA on the PCI bus. Control registers are provided to determine the source of the interrupt

  • Power Requirement
    		•  +5V, 3.3V internally, +5V, +12V, -12V current determined by IPs installed

  • LEDs
    		•  +5V, +12V, -12V and activity LEDs. 8 user LEDs also available.

  • DIP switch
    		•  An 8 position switch is available for multi-board support, to allow for configuration control or to facilitate debugging

  • MTBF
    		•  1,290,549 Hours Bellcore SR332

    cPCI2IP Benefits

  • Speed
    		•  With the direct Compact PCI to IP Bridge design featured in the cPCI2IP standard accesses to your hardware happens faster than in competing designs. Throughput is increased by an additional 50% when the 32 bit access mode is used. Fantastic for loading memory etc.

  • Price
    		•  The cPCI2IP has the low price point.

  • Ease of Use
    		•  The cPCI2IP is easy to use. A point and shoot user interface to the IP sites. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user.

  • Availability
    		•  The cPCI2IP is a popular board. We keep the cPCI2IP in stock. Send in your order and in most cases have your hardware the next day.

  • Size
    		•  The cPCI2IP is a 3U - 4HP [single slot] size Compact PCI board which conforms to the cPCI mechanical and electrical specifications. Eliminate mechanical interference issues.

  • IP Compatibility
    		•  The cPCI2IP is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the cPCI2IP. All other IP Modules which are compliant with the VITA specification can be expected to work.

  • cPCI Compatibility
    		•  The cPCI2IP is Compact PCI compliant. The cPCI2IP can be expected to work in any cPCI compliant backplane. ESD strip is incorporated into the design. EMC gasket coverage where possible around the bezel connector.



    shown populated with 2     IP Quad UART 485 cards installed.

    Ordering Information
     cPCI2IP.......... cPCI2IP standard model with Bezel IO only
    cPCI2IP-J2..........cPCI2IP standard model with J2 IO only
    cPCI2IP-IO..........cPCI2IP standard model with Bezel and J2 IO

    Extended Temperature -40 - +85C
    cPCI2IP-ET.......... cPCI2IP standard model with Bezel IO only
    cPCI2IP-ET-J2......cPCI2IP standard model with J2 IO only
    cPCI2IP-ET-IO......cPCI2IP standard model with Bezel and J2 IO

    Using the drop down menus, select your board build options and Accessory options.

    Quantity



    Engineering Kits
    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    cPCI2IP-Eng-1 .......... Hardware Support Engineering Kit includes: Board level Schematics [PDF], IP-Debug-Bus, IP-Debug-IO.

    cPCI2IP-Eng-2 .......... Hardware Support plus Driver Engineering Kit includes: Board level Schematics [PDF], Software[cPCI2IP Driver and sample application zip file ], IP-Debug-Bus, IP-Debug-IO.

    cPCI2IP Drivers.......... Software Support Only Windows®XP and 2000 or Linux compliant drivers for the cPCI2IP: cPCI2IP-XP/2000 Windows®XP/2000 driver for cPCI2IP The driver is designed to be overlayed with individual IP Module(s) driver(s). Please see the Driver manual for the specifics of writing your board interface. Please     contact Dynamic Engineering if you would like us to produce one for your IP or a third party design.


    Manuals
    Download the     cPCI2IP Manual 5/24/07 in PDF format.
    Download the PCI3IP mini-map Manual 5/22/02 in PDF format. If this is of interest a similar version can be made for the cPCI2IP.
    Download the cPCI2IP-XP/2000 cPCI2IP-XP / 2000 Driver Manual in PDF format.
    Download the Generic IP Driver for Windows® Manual in PDF format.
    Download the Carrier Group Linux Manual in PDF format.
    Download the Generic IP Driver for Linux Manual in PDF format.

    Use the Generic driver when a custom IP driver is not available. The generic driver is included with the XP/2000 and Linux drivers along with a sample user application making calls to the generic driver and an IP-Parallel-TTL.

    Please refer to the individual IP pages for driver availability. We are working on drivers for most of our IP´s. You can influence the order in which we complete them. Please let us know which one you need first.

    Related Products
    cPCI2IP Driver Win®XP & 2000 Drivers for cPCI2IP

    IP-DEBUG-IO II IP IO Connector Break-out Adapter

    IP-DEBUG-BUS IP module extender specialized for debugging

    HDRterm50 50 position terminal block with ribbon cable connector

    HDRribn50 Ribbon Cable for IP Modules with strain relief and cable pull tab

    IP-MTG-KIT Mounting Hardware for IP Modules



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