cPCI2IP

If you want to use IndustryPack® modules with your cPCI system then cPCI2IP is the choice for you. cPCI2IP combines features you need with simplicity and speed. 2 IP modules can be installed. 32 bit and double wide modules fit right in. Each position has independent operation - control, clocking, IO, power filtering and protection. cPCI2IP is highly integrated with the PCI and IP interfaces closely coupled within the same FPGA. As a result cPCI2IP is faster, has a higher MTBF, and is easier to use than competing designs. There are fewer initialization steps and fewer PCI addresses to deal with and yet there are more features to work with. With the Windows or Linux drivers operation can be "plug and play". cPCI2IP is a mature design currently revision 05 on the PCB. A planned upgrade to Spartan VI is in the works - software transparent - to provide added lifespan to this product. Dynamic Engineering launched cPCI2IP in 2002 and still supports today. Our base drivers are written to support both PCIe and PCI based IP carrriers allowing our IP drivers to be common for both bus types. This means an IP driver developed for cPCI2IP will work with PCI3IP, PCIe3IP, PCIe5IP, cPCI2IP, cPCI4IP, VPX2IP, PC104pIP etc. For newer platforms requiring PCIe please consider PCIe3IP and PCIe5IP designs.

Multi-board operation is supported. With multiple cPCI2IPs in your system and unique cabling, sensors etc. for each slot on each cPCI2IP it is important to "know" which cPCI2IP is which and to properly control the IP modules mounted to them. A surface mount "dip switch" is provided to create a programmable identifier to the software. A specific cPCI2IP can be matched up with the PCI address allocated to make for deterministic control. The switch can also be used for other purposes; configuration control or debugging for example. The switch values are available to be read via the PCI bus. The Dynamic Drivers make use of the Switch and Slot information to uniquely identify each installed IP and to associate a system "handle" with a particular module.

Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together for the slots plus the state-machine. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation across the IPs and the controlling state-machine. Clock distribution is critical for reliable operation.

Each position has resettable "self healing" fused filtered power. +5, +12, and -12V supported.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. The connectors are "wired" 1:1 from the IP IO connector to the Header connector. The Headers are numbered with standard ribbon cable conventions. The traces are matched length between the IO connector and header for each channel. Bezel and Rear IO options are isolated with 0 ohm resistors mounted back to back for "Zero" stub length. HDRterm50 can be used to create a terminal block interface. Both bezel connectors come with ejectors. The front panel is supplied with a blank bezel or the ribbon cutout version depending on the ordering option. Bezel IO models come with the "Condo Header" cutout and Rear IO models -J2 come with a blank bezel.

Slots A/B are configured to accept two single IPs, or a double wide Industrypack compatible design. The data bus is designed to allow for 32 bit IP Bus operation. The data bus width is controlled by the address range the slot is controlled with. Automatic switching makes it possible to switch data bus size without changing the control registers for seamless operation.

The IPs can be reset from the control register within the FPGA via the software interface. The IPs are reset on power-up via a supervisory circuit that guarantees the 200 mS minimum reset requirement in the IP specification. The resets only affects the IP slots. In addition IP-Debug-Bus can be used and has a separate reset button only affecting the position it is installed onto.

LEDs are provided to each of the IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LEDs [3] are provided. An additional eight user LEDs are available for debugging or other purposes.

IndustryPacks are usually 16 bit devices and the PCI bus supports 32 bits. cPCI2IP accepts 32 bit PCI accesses and converts them into two 16 bit accesses with an auto-incremented or static address. One PCI access can be used to write to or read from two IP locations or twice to one location. Byte, Word and Long Word accesses are supported to the 16 and 32 bit IP sites from the PCI bus. If a 32 bit IP has been installed then direct 32 bit operation can be utilized.

The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the cPCI2IP is created. The cPCI2IP responds normally to the host, not tying up the PCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences. Multi-threaded software operation is supported with separate bus error status in each of the slot control registers.

The PCI bus is defined as little endian and many IPs have their register sets defined to operate efficiently with a little endian interface. The default settings on the cPCI2IP are "straight through" byte for byte and D15-0 written to address 0x00 before D31-D16 written to address 0x02 when long words are written to 16 bit ports. Please note that any long word address can be used. The lower data is written to the lower address first, then the upper data to the upper address. Each slot has a ByteSwap and WordSwap control bit to allow Byte and Word Swapping to be performed to accommodate alternate IP and OS requirements.


Byte Swapping accesses to a 16 bit port.


Byte Swapping access to a 32 bit port

The cPCI2IP is a universal board design and can be used in any cPCI slot. The cPCI2IP is not keyed to allow installation into 3.3 or 5V cPCI defined slots.

Connector positioning is compatible with IP-Debug-Bus to allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the cPCI2IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.