cPCI4IP



cPCI4IP is a 6U 4HP cPCI [CompactPCI] design with 4 IP positions.
Rear IO version shown. Front Panel IO also available.


The cPCI [CompactPCI] compatible cPCI4IP design adds 4 Industrypack compatible slots to your cPCI host. The cPCI4IP acts as an adapter, converter, carrier, or bridge between the cPCI bus and your IndustryPack hardware. The cPCI4IP is a 6U 4HP cPCI design with 4 IP slots. Drivers for Linux and Windows® are available.

Each slot has a separate clock controller for 8 and 32 MHz operation. The clocks are locked together, slots plus the state-machine. Glitch free operation means the frequency can be be changed on the fly. Series and parallel terminations with equal length traces insure clean clocks and coherant operation across the IPs and the controlling state-machine. A well designed clock distribution is critical for reliable operation.

Each slot has resettable "self healing" fused filtered power. +5,+12, and -12V supported.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. The connectors ave accessible via the bezel. Ribbon cable or discrete wire cables can be interfaced directly with the cPCI4IP. Alternatively the HDRterm50 can be used to create a terminal block interface. In addition the IP IO is routed to the J4 and J5 connectors to allow backplane IO options. The J4/J5 IO is an option which can be specified with the -RP designation.

Slots A/B and C/D are configured to accept two single IPs, or a double wide Industrypack compatible design. The data bus is designed to allow for 32 bit IP Bus operation.

A local reset switch is provided for the IP boards. In addition the IPs can be reset from the control register within the Xilinx via the software interface. The reset only affects the IP slots. The PCI interface should only be reset via the backplane so that system addressing information is not lost.

LEDs are provided to each of the IP slots for activity indicators. When each slot is accessed the LED is flashed. The Xilinx provides a "one shot" circuit to stretch the "on" time to make it visable. Power indicator LEDs [3] are provided on slot D. An additional eight user LEDs are available for integration or other purposes.

A surface mount "dip switch" is available for configuration control or integration purposes. The switch values are available to be read via the PCI bus.

Most IndustryPacks are 16 bit devices and the cPCI bus supports 32 bit accesses with FAST technology. The cPCI4IP accepts 32 bit cPCI accesses and converts them into two 16 bit accesses with an auto-incremented or static address. One cPCI access can be used to write to or read from two IP locations or twice to one location. Byte, Word and Long Word accesses are supported to the IP sites from the cPCI bus.

IP Modules which support 32 bit accesses are supported with the combination of both slots A&B or C&D. The cPCI4IP automatically switches to 32 bit mode when the 32 bit access address range is used.

Byte and word lane switching are supported to provide a hardware solution when big vs little endian issues arise. Each slot has separate controls for maximum flexibility.

The IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the cPCI4IP is created. The cPCI4IP responds normally to the host, not tying up the cPCI bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have undesirable consequences.

Connector positioning is compatible with IP-Debug-Bus to allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the cPCI4IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

Coming soon is the rear panel cPCI_IPIO break out which will act like a PIM Carrier specific to IndustryPack Modules. The 6U version will have 4 50 pin connectors with 1:1 wiring from the J4/J5 connectors. The cPCI_IPIO will mount on the rear of the backplane and provide the equivalent of bezel IO on the rear. Please contact the factory for status on this project.

The IP IO connectors are available via the Bezel IO or the J4/J5 backplane IO. Because of cPCI configuration issues three models of the cPCI4IP are available. -BIO, -RP and Both. the -BIO is the default option. The bezel IO is accomplished with a pair of stacked dual 50 pin headers - 50 pin ribbon cable compatible. The J4/J5 IO is isolated with 0 ohm resistors. When the -BIO option is selected the resistors are not installed to remove the added line length. When the -RP option is selected the resistors and J4 and J5 are installed to add the IO to the rear panel. The slots are separated to allow mixed applications with some IO at the Bezel and some on the backplane. The IO are matched length between the IP IO connector and the Bezel or Rear connector. Please contact the factory for more options.

The cPCI4IP is a universal board design and can be used in any cPCI slot. The cPCI4IP is not keyed to allow installation into 3.3 or 5V cPCI defined slots.



cPCI4IP Features

  • Size
  • 6U - 4HP [single slot] cPCI card.

  • IP compatible slots
  • 4 independent slots. Slots A/B and C/D can be used together for a double wide or 32 bit IP modules.

  • Clocks
  • Each slot has independent selection of 8 and 32 MHz operation.

  • Access Width
  • Each IP Module slot can be accessed as byte, word, or long word. Long words are converted to double word accesses. 32 bit IP accesses to double wide slots.

  • Bus Error
  • The Watch-Dog timer protects against PCI bus hangs by responding when the IP is not installed or has a failure. 7.3 uS timeout. Separate status per slot.

  • Cable interface
  • Industry standard 50 pin header connectors. Bezel mount. J4/J5 IO is also available. PICMG 2.4 rev 1.0 6U IO mapping.

  • Software Interface
  • Control registers are read-writeable
    IO, ID, MEM, INT spaces supported for single and double width cards [8,16, 32 bit access].
    Windows® and Linux drivers available.

  • Space Decoding
  • Full IO, ID, and INT space decoding. Standard board supports full MEMory space decoding, -MM version has minimized [64K] MEM space per IP Module. The MM version has one eigth the PCI memory requirement of the standard board.

  • Interrupts
  • Each IP has 2 potential interrupts. All are routed to INTA on the cPCI bus. Control registers are provided to determine the source of the interrupt

  • Power Requirement
  • +5V, 3.3V internally, +5V, +12V, -12V current determined by IPs installed

  • LEDs
  • +5V, +12V, -12V and activity LEDs. 8 user LEDs. Visable from front panel.

  • DIP switch
  • An 8 position switch is available for multi-board support, to allow for configuration control or to facilitate integration



    cPCI4IP Benefits

  • Speed
  • With the direct PCI to IP Bridge design featured in the cPCI4IP standard accesses to your hardware happens faster than in competing designs. Throughput is increased by an additional 50% when the 32 bit access mode is used. Fantastic for loading memory etc.

  • Price
  • The cPCI4IP has the low price point.

  • Ease of Use
  • The cPCI4IP is easy to use. A point and shoot user interface to the IP sites. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user. Windows drivers available.

  • Availability
  • The cPCI4IP is a popular board. We keep the cPCI4IP in stock. Send in your order and in most cases have your hardware the next day - delivered to you via FedEx.

  • Size
  • The cPCI4IP is a 6U - 4HP [single slot] size cPCI board which conforms to the cPCI mechanical and electrical specifications. Eliminate mechanical interference issues.

  • IP Compatibility
  • The cPCI4IP is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the cPCI4IP. All other IP Modules which are compliant with the VITA specification can be expected to work.

  • cPCI Compatibility
  • The cPCI4IP is cPCI compliant. The cPCI4IP can be expected to work in any cPCI compliant backplane. ESD strip is incorporated into the design. EMC gasket coverage where possible around the bezel connector. With -RP models a blank bezel with full gasket coverage is provided.


    Ordering Information
    cPCI4IP.......... cPCI4IP standard model with Bezel IO only (-FP)
    cPCI4IP-RP..........cPCI4IP standard model with J4/J5 IO only
    cPCI4IP-IO..........cPCI4IP standard model with Bezel and J4/J5 IO
    cPCI4IP-MM.......... cPCI4IP Mini Map model with Bezel IO only
    cPCI4IP-MM-RP..........cPCI4IP Mini Map model with J4/J5 IO only
    cPCI4IP-MM-IO..........cPCI4IP Mini Map model with Bezel and J4/J5 IO

    If your system needs some front and some rear IO and you do not want the extra length associated with the -IO model please note that you can order mixed slot IO versions - 1, 2, 3 or 4 slots to the bezel and the rest to the rear. [0-4,1-3, 2-2, 3-1.4-0] Most users select the 4-0, 0-4, or the 4-4 option which we stock. The other options are by special order.

    Extended Temperature -40 - +85C
    cPCI4IP-ET.......... cPCI4IP standard model with Bezel IO only
    cPCI4IP-ET-RP......cPCI4IP standard model with J4/J5 IO only
    cPCI4IP-ET-IO......cPCI4IP standard model with Bezel and J4/J5 IO
    cPCI4IP-MM-ET.......... cPCI4IP Mini Map model with Bezel IO only
    cPCI4IP-MM-ET-RP..........cPCI4IP Mini Map model with J4/J5 IO only
    cPCI4IP-MM-ET-IO..........cPCI4IP Mini Map model with Bezel and J4/J5 IO

    Using the drop down menus, select your board build options and add on options.

    Quantity


    Engineering Kits
    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture.


    Manuals
    Download the
    cPCI4IP Hardware Manual 10/17/16 in PDF format. Full IO, ID, INT, MEM spaces
    Download the cPCI4IP mini-map Manual 10/5/07 in PDF format. Full IO, ID, INT plus 64K MEM space version of cPCI4IP
    Download the IP Carrier Windows®7 manual. For PCIe and PCI based carriers
    Download the Win7 Generic IP Driver Manual in PDF format.
    Download the Carrier Group Linux Manual in PDF format.
    Download the Generic IP Driver for Linux Manual in PDF format.

    Download the Letter of Volatility in PDF format.

    Use the Generic driver when a custom IP driver is not available. The generic driver is included with the Windows® and Linux drivers along with a sample user application.

    Please refer to the individual IP pages for driver availability. We are working on drivers for most of our IP´s. You can influence the order in which we complete them. Please let us know which one you need first.


    Related Products
    IP-DEBUG-IO II IP IO Connector Break-out Adapter
    IP-DEBUG-BUS IP module extender specialized for debugging
    HDRterm50 50 position terminal block with ribbon cable connector
    HDRribn50 Ribbon Cable for IP Modules with strain relief and cable pull tab
    IP-MTG-KIT Mounting Hardware for IP Modules


    Custom, IP, PMC, XMC, PCIe, PCI, cPCI, PC104p, PCIe104, VME, VPX Hardware, Software designed to your requirements



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