HOTLink is used in applications demanding high speed and high reliability including sonar, radar, other scanning applications, seismic, oil exploration etc. Alternate purposes would include high speed buses between equipment or within equipment for command and control, data transfer etc. PCIe4LHOTLinkX6 is a PCI Express card with 6 HOTLink receiver/transmitter pairs. Each of the HOTLink channels is supported with a separate DMA transfer engine plus local memory. The lower 4 channels are 1/2 duplex and the upper 2 full duplex. The standard version has many triggering / transfer control programmable features to allow start of frame sequences, end of frame sequences, synchronized start across channels, constant [programmed] delay between frames [indepedent each channel].
The HOTLink protocol implemented provides positive emitter coupled logic (PECL) or LVDS data inputs and outputs. The transmit byte rate is determined by the programmed frequency of the PLL clock output. This clock is multiplied ten times by the HOTLink transmitter to send the transmit byte data stream which is expanded to 10 bits by the internal 8B/10B encoder. The PLL is programmed via software over a serial I2C interface.
Up to six independent HOTLink channels are provided per card. The base design implemetation has programmable frame definitions - which K´s are used to start a frame and end a frame. The start and stop are further programmable to be up to 3 K´s in series with the same or different values for each. Interrupt options are provided to support frame capture nad movement to the host memory.
The initial design implementation used PCIe4LHOTLinkX6 with 4 channels to capture RADAR data. The data formatting was unknown at first. The SW option to store all was selected along with the option to store the K´s as well as the data. The K characters are converted and flaged. After reading through the data the start sequence was deduced and used to synchronize to the data stream. Data packing could then be enabled in which case the null´s and other K characters are removed and the byte data packed into 32 bit words. In many cases the base design can be used to meet your needs. If you need a more specific implementation please contact Dynamic Engineering with your requirments.
PCIe4LHOTLinkX6 utilizes a Spartan 6 100 FPGA. The FPGA allows for a lot of internal memory and complex data manipulation in HW. The memory is typically used for FIFO´s or RAM. The FIFO´s can be accessed by single-word [target] read/writes as well as DMA burst transfers. A FIFO test bit in each channel control register enables the data to be routed from the transmit to the receive FIFO for a full 32-bit path providing loop-back testing of the FIFO´s. The channels are supported with 12 independent DMA engines. A local arbitration unit keeps everything moving efficiently. DMA transfers can be programmed for any size transfer from very small to multiple megabytes using the scatter gather capable programming model.
All parts are industrial temp or better [-40C <=> +85C]. Conformal coating, is available to help adapt to your environment.
PCIe4lHOTLinkx6 Block Diagram