PCIeAlteraCycloneIV





User Configurable Logic - PCIe Altera Cyclone IV 485/LVDS comes with everything you need to load your Altera program into the Cyclone IV. Fantastic for development, simulation, special purpose interfaces, multiple serial and / or parallel channels. FLASH and on-the-fly reloading for configurable and reconfigurable logic implementations.

PCIe compatible PCIeAlteraCycloneIV-485/LVDS design is for the advanced user who wants to implement their own Altera design or requires updatable logic. PCIeAlteraCycloneIV makes the implementation, and use of the Cyclone IV easy.

The design comes with the basic features built in and the specific features ready for you. The Xilinx FPGA takes care of the PCIe interface for initial loading of the Altera, and DMA transfer of data into and out of the FIFO´s. The Altera FPGA controls 40 programmable RS-485 or LVDS transceivers and 12 TTL IO. Each of the RS-485 or LVDS channels is programmable for direction, termination and function. The 12 TTL IO can be inputs or outputs. Eight Cypress 22393 PLL´s support the Altera providing the ability to synthesize multiple reference rates. The only thing missing is your input in the form of a coprocessor, reconfigurable logic, state-machine, simulated system, asynchronous or synchronous data processing etc.

A TSI384 is used to bridge between the 4 lane PCIe interface and the Xilinx Spartan 6 FPGA. Together the TSI384 and Spartan 6 are used to move data to the Altera for output channels, and to move data to the host for input channels. 8 input and 8 output FIFO´s are provided to support 8 bi-directional channels. The intermediate FIFO´s are byte wide and operate at 66 MHz between the Spartan 6 and Cyclone IV. Each of the data paths has its own DMA controller and local arbitration to move data from the Altera through the Xilinx to the the PCIe lanes or vice-versa. In addition a control bus is provided - 32 data, 12 address, 33 MHz to provide a method of programming registers or memory within the User Design. An interrupt request from the Altera through the Xilinx is provided.

IO is accomplished via RS-485 or LVDS transceivers or TTL buffers. The RS-485 transceivers are rated for 40 MHz. The LVDS is rated for 200 MHz. Each transceiver can be controlled for direction and termination. The TTL IO is implemented with ´125 open drain drivers with on-board pull-ups. The input direction is buffered with a receiver to protect the Altera and to provide level shifting between the 5V IO and the 3.3V Altera IO. The D100 [ SCSI II 100 pin connector ] provides an easy to interconnect cabling system. The pinouts are consistent with the industry standard differential pairings. The HDEterm100 supports the D100 with a cable to terminal strip conversion.

An 8 position dip switch is provided. The switch is read through the Xilinx. The switch can be used to distinguish multiple PCIeAlteraCycloneIV boards in the same system or for other user determined purposes.

LED´s are provided. 4 are controlled via the Altera and the user design. Others are provided to show the power suppies are within tolerance. The LED´s can be used for debugging or for system status etc.

Software [Windows® driver] to load the Altera, access the hardware, and run diagnostics is available as well as a reference design for the Altera which controls the byte lanes, IO, and PLL´s. The drivers come with standard calls for the standard features plus a generic R/W interface to allow for any user update without needing driver modifications. Many of the reference software files use the generic IO control to show how this is done. We provide a plug ´n play set-up along with our ATP software to give you a running start at your design.

We can do the design implementation for you, and provide the design files to you for long term support. If you need the features of the PCIeAlteraCyclone IV and prefer to have someone else do the programming, please contact us with your requirements.



PCIe Altera Cyclone IV 485/LVDS Features

  • Size
  • Small size PCIe card.


  • Altera
  • Cyclone IV 115 EP4CE115F29(I,C)8 standard.


  • Clocks
  • 133.333 MHz reference oscillator and 33 MHz. reference clock connected to Altera. 8 Cypress 22393 PLL´s are controlled by the Altera. Each with 3 programmable clocks. Each PLL has a separate reference. 12 PLL clock inputs to the Altera are routed to Altera Clock Inputs.


  • PCIe Bus
  • 4 lane PCIe bus interface.


  • Cable interface
  • D100 connector provided with differential pinouts.


  • IO
  • 40 - 40 MHz. capable RS-485 or 40-200 MHz LVDS plus 12 TTL IO are provided. Additional TTL IO can be provided by removing some Differential IO.


  • Software Interface
  • Control registers are read-writeable. Xilinx provides mechanism to download Altera implementation.


  • Interrupts
  • Multiple programmed interrupts are available and more can be user defined. Status register provided to determine cause of interrupt. Polled operation with interrupt masked.


  • Power Requirement
  • +12V and 3.3 from PCIe interface, other local voltages converted on card.


  • LED´s
  • 4 user LED´s plus Lane Activity [PCIe] and Power Good from voltage monitor circuits.


  • DIP switch
  • An 8 position switch is available to allow for configuration control or to facilitate debugging

  • MTBF
  • TBD Hours Bellcore SR332 MTBF

  • Statement of Volatility
  • Download PDF here


  • Humidity
  • PCIeAlteraCycloneIV-485/LVDS is a standard industrial grade board, able to handle the usual 10-90% non-condensing humidity rating. If you need to have a board used in a more harsh environment, ask to have humi-seal after final test. "-CC" You may also want to elect the Industrial Temp rating Altera device.

    PCIeAlteraCycloneIV-485/LVDS Benefits

  • Speed
  • Direct DMA access to the hardware using the industry standard TSI384. 40 MHz RS-485 or 200 MHz LVDS. 16 rate matching FIFO´s for full support of 8 bi-directional serial or parallel data channels. Altera EP4CE115F29I8. [larger parts and different speed grades are available by special order] The hardware can sustain high speed operation on multiple IO channels.


  • Price
  • PCIeAlteraCycloneIV-485/LVDS is a generic board which can be shaped for your needs. It is off-the-shelf and much lower cost than developing your own PCB, loader software etc. Quantity discounts are available making it the way to go for your production requirements too. Once your implementation is "nailed" we can do a specific version for you with minimized or expanded features.


  • Ease of Use
  • PCIeAlteraCycloneIV-485/LVDS is easy to use. Just plug in and download your implementation. The engineering kit comes with support to load the Altera, and run basic tests on the hardware, break-out box and cable.


  • Availability
  • PCIeAlteraCycloneIV-485/LVDS is available either off-the-shelf or with a short lead time for the commercial version. The -ET version may have some lead time depending on device availability.


  • Size
  • PCIeAlteraCycloneIV-485/LVDS is a half size PCIe board which conforms to the PCIe mechanical and electrical specifications. Can be used in 4 lane or larger PCIe connectors.


  • PCIe Compatibility
  • PCIeAlteraCycloneIV-485/LVDS is PCIe compliant. PCIeAlteraCycloneIV can be expected to work in any PCIe compliant backplane. PCIeAlteraCycloneIV has been tested in multiple PC systems from various manufacturers.




    Ordering Information
    PCIeAlteraCycloneIV Add the following options to the base part number to build your ordering option
    -485.............................485 IO version
    -LVDS.........................LVDS IO version
    -V................................Alternate verticle connector installed for internal wiring
    -ET.............................Upgrade Altera device to Industrial temperature. All other components are always Industrial temperature.
    -CC.............................Add Conformal Coating
    -ROHS.......................Change to ROHS compliant processing


    PCIeAlteraCycloneIV-mixed................Mix the LVDS and 485 IO. The standard 485 are 5V parts and the LVDS is 3.3. When used in the mixed mode the 485 parts will be replaced with 3.3V devices. The 3.3V devices [485] have less bandwidth than the 5V. Please contact the factory to provide the channel counts that you require. A new -# will be created for your version.


    Engineering Kits

    PCIeAlteraCycloneIV is supported with Software[Driver and sample application ] XP, Win7, Linux are options. The XP and Linux driver/UserAp are the currently released versions. The drivers include a general purpose call for the GPB bus allowing the user to completely remap the Altera design [should they want to] without needing a new driver. Existing driver and reference SW for PCIeAlteraCycloneIV are included with your purchase of PCIeAlteraCycloneIV. Software products are supplied AS-IS. In addition the VHDL reference design is available to PCIeAlteraCycloneIV clients at no charge. For integration support with your project Dynamic Engineering offers
    Technical Support Packages.

    Other recommended accessories include HDETerm100-ENG, and HDECable100. HDEcabl100 mates with the D100 connector on PCIeAlteraCycloneIV and provides a shielded twisted pair connection to your electronics. The signals can be broken out with HDEterm100 or a custom cable can be designed and manufactured for you. Please contact Dynamic Engineering with your cable requirements.

    PCIeAlteraCycloneIV Options

    Manuals
    Download the
    PCIeAlteraCycloneIV HW Manual RevA in PDF format.
    Download the PCIeAlteraCycloneIV Linux Manual Rev 1.0.0
    Download the PCIeAlteraCycloneIV Win7 Manual Rev A


    Block diagram of VHDL design included with Hardware Support Engineering Kit.


    The VHDL source code for the design shown in the block diagram is included in the Hardware Support Engineering Kit. The design is a good starting point for many user designs. The design includes all of the basics that you will need : Bus interface to GPB, memory interface to FIFO´s, PLL, TTL, and Differential IO, termination and direction control. Dynamic Engineering uses this design along with the driver and Userap.exe program [source for Userap.exe included in Software support Engineering kit] to test the PCIeAlteraCycloneIV design.


    Download the CyberClocks R2.01.00 software
    right click on the above link to download and save the cyberclocks zip folder to your target. 22393 is the device type. Newer versions may be available on the Cypress website.


    Try before you buy program


    Custom, IP, PMC, XMC, PCIe, PCI, cPCI, PC104p, VME, VPX Hardware, Software designed to your requirements



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