Made in USA
The Embedded Solutions Experts


PMC Module with Spartan 6 FPGA, PLL, 32/34 Independent Differential IO - RS422, RS-485, LVDS

Order This Item
Feature Coming Soon

PMC-BiSerial-VI Description

  • Driver included with purchase
  • Standard PMC module
  • 32/33 with DMA operation
  • 34/32 independent differential IO. Each with programmable termination and direction.
  • RS-485, RS-422, LVDS and mixed
  • Bezel and/or rear IO
  • Spartan 6 FPGA with BRAM for FIFO or RAM implementation
  • PLL with 4 clock references
  • 1 year warranty standard. Extended warranty available.
  • Extended [Industrial] Temperature standard.
  • ROHS and Standard processing available
The PMC BiSerial family has been updated to include a Spartan 6 [Xilinx] based card with expanded capabilities. BiSerial VI includes industrial temperature components, and more internal RAM, clocks and gates for more complex designs. Building on the knowledge and experience gathered from multiple IP and PMC BiSerial implementations and adding in the latest technology has created PMC-BiSerial-VI. BiSerial VI features completely isolated FIFO´s with 32 bit ports for increased adaptability and performance. The FIFO´s can be configured to support RX or TX or both directions. The [34] RS-485 / LVDS buffers have individual programmable termination, and direction controls allowing for any combination of "In´s and Out´s". Half-Duplex, Full-Duplex and uni-directional systems can be configured with software and VHDL. The denser, faster FPGA will implement the most complex state-machines.

The 34 IO can be configured to support one function, one function replicated several times, or multiple functions. For example the "RL1" has 8 UART channels, while the "ORB2" has 8 channels with 4 different functions. A real space saver when you need to have some Manchester to go with your UART and HDLC ports. A partial list of functions implemented in "Channels" includes: Manchester, Miller, SDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive. To support the functions the designs include: memory elements instantiated with FIFO, Dual Port RAM, register files, as well as state-machines, counters, timers, dividers, registers, CRC and Parity generation / checking, software drivers and applications, DMA [direct memory access] and the glue that goes with it. Our designs are all written in VHDL and done in a heirarchy allowing direct porting of different features to create new implementations.

More than 30 customerized versions of the PMC-BiSerial family and counting. PMC BiSerial VI is recommended for new designs.

The hardware has been used to interface with a wide variety of equipment. What do you need to communicate with? Control? Capture data from? Please see the bottom of this page and other BiSerial implementations for descriptions and manuals for our customerized versions. We have been doing custom versions of the BiSerial since 1998 when the IP version first came out. We will be doing custom versions in the future with the next generation parts and features.

A new custom version can be implemented in a very reasonable time. Typically 2-3 weeks of design time for a medium sized project including the new VHDL set, Windows® or Linux or VxWorks driver, reference software package, and documentation. Examples of the designs performed to date are listed toward the bottom of this page and pages for previous versions of BiSerial. Click here or or scroll down to see if the configuration you need already exists or if we need to work on a custom version for you.

We can be rapid with our response because the designs are structured to allow channels to be moved in and out to create new design sets. Most designs have a fairly large component of reused "known good" VHDL that we can pull from allowing us to focus on the new functions required for your implementation. You are getting the benefit of many man-years of design and test time with each new version created. Join our high reliability clients by taking advantage of our know-how to help speed your project to completion.

PMC-BiSerial-VI can be used along with a PCIe or other carrier/adapter to use with a variety of system types - PCI, PCIe, PC104p, VPX cPCI, etc.. Dynamic Engineering has PMC carriers for PCI, PCIexpress, cPCI, PC104p, and can do custom design´s specific to client requirements as well. Please use the handy JAVA pull-down menu at the top left of any page to navigate to other Dynamic Engineering products including carriers.

PMC´s are independently specificed through VITA for the form factor, connectors and pinouts of the PCI signaling; you can use the PMC BiSerial VI design with any carrier from any vendor that supports standard PMC´s. To make it even easier the PMC BiSerial VI has a universal PCI design to allow operation with VIO set to 3.3 or 5V.

It all starts with the PCB [Printed Circuit Board]. Quality design and quality materials are required to meet the strenuous requirements of many of our implementations. You can do the job quickly or you can do the design correctly. We pride ourselves on taking the time to put the extra work into our layouts. The quality goes in before the parts go on. In addition to routing strategy and layer counts, Via size, plating requirements, break-out trace widths, and materials are areas where quality comes into play. The via size and method of trace attachment to the via affect the signal shape and reliability. Using tear-drop trace connections to pads, via´s and through hole components enhance the reliability and minimize the impedance discontinuity resulting in a cleaner signal. Using 10/12 mil vias provides adequate copper for proper power distribution and more surface area to bond to where traces are interconnected. The combination provides better vibration endurance than smaller vias and traces would provide. The design has several power planes with sufficient copper weight and coverage to provide the references required for the routing plus the current and voltages needed by the various devices on the board. The larger features make the design work more difficult since there is less room to "play with" and the end result is worth it. Since 1998 when the IP BiSerial was introduced, the BiSerial family has enjoyed an excellent track record for reliability.

The PCI interface has a published set of requirements for compliance which restrict length, impedance, loading and other factors. PMC-BiSerial-VI is compliant with the PCI Specification. The IO section has requirements based on the IO type and the purpose for the IO. A very conservative approach has been taken to allow operation with any client requirement. The IO can be LVDS or RS-485. The IO on the connector side is differential with a 100 ohm impedance requirement. Between the FPGA and the tranceivers the IO is single ended. Each IO has separate direction, termination, and data lines to allow complete flexibilty. The design has matched length connections from the FPGA ball to the seating plane of the connector. The lengths are matched to the "mil". The Impedance is controlled and the signals routed with proper spacing to avoid cross talk etc. The other features including memory, PLL, oscillator, and power supplies are implemented within the PCB to exceed the operational requirements for those devices.

The Spartan VI has internal block RAM which can be configured in a variety of ways. Currently, up to 268 BRAMs can be configured for internal channel memory support. In addition the memory can be configured as Dual Port RAM to allow direct addressing and retransmission of repeated patterns.

Sometimes you just need more memory. Two external [to the FPGA] FIFO´s are available with 128Kx32 each. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. Internal loop-back is supported. The loop-back test can be used for BIT and for software development. Programmable FIFO flags are supported on both sets of FIFO´s. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any depth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling. In addition DMA can be programmed to fill or empty the FIFO with sizes larger than the FIFO size. The DMA is hardware controlled to be held off when no data is available or no room is available. With the "Channelized DMA"™ capability and large FIFO´s the software application can have reduced interrupt counts to deal with while supporting larger and faster IO transfer rates.

PMC-BiSerial-VI has 34 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PMC-BiSerial. RS-485 transceivers support up to 40 Mhz rates. The LVDS transceivers are rated at better than 200 MHz.

The IO is available through either the front panel mounted SCSI III connector or Pn4 or some combination. Each transceiver pair is isolated from the connector with zero ohm resistors. The resistors are mounted front and rear and tied together at each pin to allow for a stub length of 1/16th in. The Connectors are routed from the resistor packs directly allowing for almost zero stub lengths and the option to connect front or rear IO options. In addition the IO have resistors tied between the IO and a power plane. The plane is strappable to allow 5V or GND on either rail. The IO can be set to provide a high or a low condition when not driven to support half duplex operation without adding resistors to your cables.

Clock options are frequently a major factor in embedded designs. Getting the right reference to the right part of the design and allowing for local control of exact frequencies. PMC BiSerial VI has a PLL with 4 programmable outputs, reference oscillator, internal DCM´s and buffering plus programable dividers instantiated within the VHDL. The PLL can be programmed to "any" fixed frequency, the DCM used to create phase variations, and local dividers to allow on-the-fly channel based frequency changes.

"Channelized DMA"™ is an important feature of the PMC-BiSerial-VI design. With "Channelized DMA"™ you have a separate DMA engine for each transmitter and each receiver within each channel. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency.

If your situation demands a custom application we will update the Xilinx FPGA and IO components. Send us your timing and we will send you the interface. Please refer to the bottom of this page for previously completed "customerized" PMC BiSerial VI implementations.
email us your wish list or call today

PMC-BiSerial VI Example Block Diagram

PMC BiSerial VI ORB2 version block diagram
PMC Modules require a "carrier" in most cases to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats.
PCIe implementations can be done with the PCIeBPMCX1 and PCIeBPMCX2.
PCI implementations can be done with the PCI2PMC and PCIBPMCX2.
cPCI 3U is supported with the cPCIBPMC3U64
cPCI 6U is supported with the cPCIBPMC6U.
PCI-104 is supported with the PCI104p2PMC.

PMC-BiSerial-VI Features

Std PMC 74mm x 149mm nominal. Low profile components on rear
IO is available via the PMC bezel connector and / or the PMC "user IO" connector Pn4. The differential IO is properly routed with impedance control, pitch, and space plus matched lengths across all of the pairs. 0 ohm resistors are used to isolate the front and rear panel IO to allow single port designs to remove the bus stub to the removed port. Please note that the lower 32 channels [only] are routed to Pn4 due to pin limitations. Differential pairs match Dynamic Engineering PMC Carrier Differential Routing standard to allow high speed [when needed] operation. Up to 50 MHz with RS-485 and up to 200 MHz with LVDS IO types.
33 MHz PCI, 50 MHz oscillator ( other frequencies available), 4 programmable PLL inputs, Counters / Dividers / DCM for local clock control.
Interface Types
Custom programmed interfaces are available. Please send us a timing diagram, and we can program one for you. Most interfaces can be adapted from our large library of designs within 2-3 weeks including the updated VHDL, Windows or Linux or VxWorks Driver, reference manuals etc. We can support on-site [ours] integration to help you get your application level software working.

Alternatively choose one of the already completed versions and purchase off-the-shelf. Common requested and implemented interface types include: Manchester, Miller, SDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive. Mix and Match. Just like but different...
Spartan 6 - 100 is standard and has 268x1Kx16 BRAM´s to create RAM, FIFO etc., Optional discrete (2) FIFO´s -128K x 32 are available.
Software Interface
Control registers are read-writeable
Windows®, Linux, VxWorks reference SW and Drivers
Software programmable interrupts on status, errors, completion of transfer, DMA, FIFO levels, custom events. Status can be polled for non-interrupt driven operation as well.
Power Requirement
+5V converted to 3.3V, 2.5, 1.2 with local DC:DC power supplies for efficient power conversion. 1.8V for FLASh with linear regulator.
On rear indicating Main DC/DC [3.3V] is in regulation.
TBD million hours. Bellcore. GB 25c

PMC-BiSerial-VI Benefits

PMC-BiSerial-VI can offload your CPU and increase system speed. The IO rate is high compared to typical IP Module uses allowing for system upgrades, replacement of older boards, and relocating processes done in SW to the HW as needed.
System level cost is best when reasonably priced reliable hardware is used and NRE minimized. With PMC-BiSerial-VI, driver support for the carrier and IP level, reference software, history of reliable operation, and fantastic client support your cost per unit and overall costs are attractive.
Ease of Use
PMC-BiSerial-VI is designed to be easy to use. Direct access to all features, aligned registers for larger access types, programmable features to allow personalization for your system. Please download the manuals and see for yourself. Reference software is provided in source form to get you started.
There are two basic models with LVDS or RS-485 IO types. Both are stocked allowing a quick "PCO" to reflash and retest into your configuration. Already completed designs can be ordered with a minimal delay in delivery. New NRE required designs will have some delay to implement, integrate and test.
PMC Specification Compatibility
PMC-BiSerial-VI is compliant per the VITA PMC/CMC specifications. Tested with PCI and PCie based carriers. All Dynamic Engineering PMC Modules are compatible with the PCIeBPMCX1, PMC-BiSerial-VI will operate with any PMC specification compliant carrier board.

Part Number: PMC-BiSerial-VI
Ordering Options

  • PMC-BiSerial-VI Standard board - with RS485 IO , Industrial temperature components.
  • -LVDS Switch to LVDS IO
  • -ROHS Use ROHS processing. Standard processing is ""leaded"
  • -CC Option to add Conformal Coating
  • -XXX See Manuals section for customized versions and replace XXX with type "UART" for example

PMC-BiSerial-VI Drivers

Software Support for PMC-BiSerial-VI-XXX includes: Windows® 7, VxWorks, and Linux compliant drivers
Please see the Driver manuals for the specifics of each type.

Drivers and Reference SW are developed for each type / version of PMC-BiSerial-VI implemented. When custom versions are ordered the NRE will include providing Windows, Linux, and or VxWorks packages. For off-the-shelf models, select on the manuals tab, the Windows® and Linux SW shown is included with your purchase of the HW. A small one-time charge is required for the VxWorks versions. Unsupported SW versions may have an NRE requirement.

Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.

PMC-BiSerial-VI Models


Customer: ADI
8 UART I/O ports each consisting of RS-485 transmit and receive data. [LVDS is an ordering option] The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the port reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Reference clock for each port is selectable between the 32 MHz reference and a user programmed PLL frequency. Each UART port has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFO´s. DMA support on all channels. 5 modes can be selected per fully independent node: Standard UART (unpacked), Packed, Packetized, Alternate Packetized, and Test. Options for Bezel and Rear IO.

  • UnPacked mode 8 bit data is assumed mimicking standard UART operation
  • Packed mode 32 bit data is assumed allowing 4 characters to be read/written at a time.
  • Packetized mode allows for non-LW data lengths, and retains most of the efficiency of LW packing. Odd lengths [non LW boundaries] are loaded with the complete LW´s first then the remainder. The Packet length FIFO is programmed with the length to send. The Packet lengths can be loaded to transmit with minimal HW delay between Packets or with a programmed delay.
  • Alternate Packetized mode uses 3 bytes per LW and has the packet descriptor information built into the 4th byte.
  • Test mode SW controls the output pattern to allow for programmed errors on certain characters sent.

  • Programmable timers are available to control the time between packets sent and as a master timer to start new bursts of packets. In addition the Alternate Packet mode supports automatic tristate control and automatic transmit enable/disable to support the packet burst timing. Please see the HW manual for more information.

    Download the PMC BiSerial VI UART Hardware manual.
    Download the PMC BiSerial VI UART Windows Driver manual.
    Download the PMC BiSerial VI UART Linux Driver manual.