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PCI-SpaceWire

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PMC-SpaceWire Description

  • Windows®, Linux, or VxWorks driver available with purchase
  • DMA on all channels
  • 4 channels each with 1 transmitter and 1 receiver. BK models 200 MHz rated.
  • Time Code support
  • Two SW models: Standard and the new enhanced BK version
  • 1 year warranty standard. Extended warranty available.
  • ROHS and Standard processing available
Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-ST-50-12C specification. SpaceWire is configured using routers to create a heirarchical point-to-point system with high speed parallel paths.

PCI SpaceWire implements SpaceWire in a convenient PCI format. With PCI-SpaceWire the four channels fit on the Bezel. The SpaceWire specification calls for LVDS signaling and a specific 9 pin micro-D connector. You can connect PCI-SpaceWire to other SpaceWire compliant devices without electrical interface issues.

Four fully independent and highly programmable LVDS IO channels are provided by the PCI-SpaceWire design. In the SpaceWire implementation the channels pass tokens between two independent state-machines to provide the proper protocol. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point. With the SpaceWire protocol it is easy to build a heirarchical architecture system with routers or a home-run wired system. Your equipment can interact with any other node in the system. PCI-SpaceWire provides a bridge from PCI <=> SpaceWire. Channel based DMA offloads your CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the manuals at the bottom of this page for detailed information

Each channel has FIFO memory with 4[K]/64K[BK] Kbytes TX and 4[K]/64K[BK] bytes RX standard with an option for an additional 512Kbytes. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. The base FIFO´s are internal to the FPGA and utilize dual ported RAM configured as a FIFO. Two external positions are available for larger FIFO´s to be installed to support one of the channels in both directions or two of the channels in one direction.

The interface is optimized to minimize the latency on the PCI bus. The loop-back test can be used for BIT and for software development. The programmable FIFO flags are supported for interupt driven or polled operation. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size.

SpaceWire features automatic link testing when a node is brought on line - released for operation via software. The transmitter sends NULLs until NULLs are received and then sends FCTs until FCTs are received. The initial frequency is specified [ECSS-E-ST-50-12C] to be 10 MHz. Once the auto link test has passed, the hardware can switch to the programmed rate. A local oscillator is used to supply the 10 MHz reference clock for initialization. A programmable PLL is used to support operation once the link is established. The PLL is programmed via software and is referenced to the oscillator.

The SpaceWire protocol has flow control. The local memory on the PCI-SpaceWire will not overrun. In situations where the data being sent to the PCI-SpaceWire card is not buffered it is recommended to use a "-128" model with large FIFO´s on channel 0. The issue is upstream - if there is an unbuffered or under-buffered data source that will loose data if the link is throttled back the larger FIFO´s will help. The larger FIFO´s will provide more room to accumulate data if the system is not ready to allow the PCI-SpaceWire to DMA transfer it immediately. The DMA transfers are higher bandwidth than the SpaceWire transfers allowing the system to catch-up once the DMA transfers restart. At 100 MHz and 80% data transfer the 128x32 FIFO will provide about 52 mS of data storage. The host would have to ignore the PCI-SpaceWire interrupt requests for longer than 52 mS before throttling would occur. In most systems this is sufficient time to stay out of the throttled mode. To unload a full FIFO with DMA running it will take 128K/33M = .4mS => the unload to load multiplier is stongly in favor of the host side allowing the host to catch-up to the SpaceWire link once the delaying event has passed.

With the 10-2006-0103 and later PCB´s, PCI-SpaceWire uses a Spartan 6 FPGA. The revision "K" design has been ported to this FPGA and will be the default FLASH program going forward. New versions of the card will have an additional "-BK" Beyond K added to the part number to make sure orders for current systems are filled with compatible HW. New features are planned to make use of the new larger Industrial Temperature FPGA. All 10-2006-0103 and later boards will be Industrial Temperature as a standard feature. Features include larger internal FIFO´s, [planned]error injection, rearranged memory map to make room for additional features, wider counters and more options for interrupts. Please send in your requests for added features.

Model -BK is recommended for new projects and projects that want an upgrade. The K revision will continue to be available for any current projects.

PCI-SpaceWire is supported with the DESWBO Dynamic Engineering SpaceWire BreakOut tool for debugging SpaceWire systems, cables, and the DESWCB Dynamic Engineering SpaceWire Connector Board which provides a SpaceWire Cable to system cable interface.

If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

PCI-SpaceWire Block Diagram

Model K diagram shown



The standard timing uses the data and strobe to transmit and to receive the data. The data is transmitted as a command or data. The strobe provides the transitions for clocking when the data is unchanged between adjacent bit times.

PCI-SpaceWire Standard Timing

PCI-SpaceWire Features

Size
1/2 length PCI
Transmit Speeds
10 MHz initial rate per SpaceWire Specification. Software selectable secondary rate for transmit channel. Max. [K]frequency currently 180 Mhz. BK models rated at 200 MHz. Oscillator and programmable PLL combined for user frequency support.
PCI Speed
Standard 33 MHz. operation. DMA support or standard R/W operations, DMA is independent per channel - each channel has a separate controller to allow long data transfers with minimal CPU overhead and increased performance.
PCI Access Width
Standard 32 bit operation supported
Software Interface
PCI registers are read-writeable. Transmit and Receive functions separated.
Interrupts
Transmit and Receive state-machines, FIFO Programmable almost empty [transmit] and programmable almost full [receive] have programmable interrupts. Status can be polled for non-interrupt driven operation as well. Time Code interrupt.
Signaling
LVDS interface devices are utilized.
IO Interface
IO is available [4 ports] via the PCI bezel connectors. The differential IO is routed with controlled impedance, and matched lengths on each of the pairs. 9 Pin MDM connectors as specified in ECSS-E-ST-50-12C.
Interface
ECSS-E-ST-50-12C specification compliant. Time Code supported.
Specification
PCI specification compliant
Power
5V and 3.3V from PCI connector with 2.5V, 1.2V, (1.8V) converted with on-board regulators.
Memory
Separate FIFO´s are provided for TX and RX of each channel. Internal Block RAM creating 4K[K model] 64K[BK model] is standard for all channels. 128K x 32 is available on port 0. Add -128 to part number for this option -128RX uses the external FIFO´s for port 0 and port 1 RX path.
Statement of Volatility
DIP switch
An 8 position switch is available to allow for configuration control, multiple PCI SpaceWire boards, and to facilitate integration

PCI-SpaceWire Benefits

Speed
PCI-SpaceWire is optimized for serial interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the PCI-SpaceWire has independent and interconnected port functions. All ports can operate at maximum rate in parallel.
Price
PCI-SpaceWire is available off-the-shelf at a reasonable price. Custom versions can also be arranged. PCI-SpaceWire is easily programmed to implement new functions. Previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. A modified SpaceWire will represent a large cost and time savings in your budget.
Ease of Use
PCI-SpaceWire is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and reference software help with integration into your system. Windows® Linux, and VXWorks driver(s) and reference SW are available.
Availability
Dynamic Engineering works to keep PCI-SpaceWire [K and BK] in stock. Send in your order, and in most cases have your hardware fast. With custom designs a few week design period is usually required. We can support immediately with the std version, then send updated FLASH files later to help get your project going - right away.
Size
PCI-SpaceWire is a standard 1/2 length PCI card, and meets the PCI mechanical specifications. PCI-SpaceWire can be used in all PCI positions [universal voltage]
PCI Compatibility
PCI-SpaceWire is PCI compliant.

Part Number: PCI-SpaceWire
Ordering Options

  • PCI-SpaceWire Standard board - Standard version with 4Kb FIFO per channel, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Four(4) channels through the Bezel.
    Order combinations of the options by simply adding the extension(s) to your order request.
  • -128 - Standard version with 4Kb FIFO per channel plus 512K [128K x 32] FIFO´s added to port 0 [TX and RX], standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support.

    -128RX - Standard version with 4Kb FIFO per channel plus 512K [128K x 32] FIFO´s added to channel 0 and 1 on RX, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support.

    -BK - BK version with 64Kb FIFO per channel, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Updated version recommended for new designs.

    -CC - add Conformal Coating
    -ROHS - add ROHS processing

PCI-SpaceWire Drivers

Software Support is supplied in the form of Win7, Linux, and VxWorks packages. The manuals are available on the SpaceWire Summary page.




PCI-SpaceWire Manuals

Hardware. The Hardware manuals for K amnd BK models plus related products are available on the SpaceWire Summary page.