PC104p-SpaceWire
PC104p and PCI-104 Compatible SpaceWire Interface

PCI-104-SpaceWire Shown




Utilize SpaceWire to communicate with the European Space Agency and NASA equipment utilizing the ECSS-E-ST-50-12C specification. SpaceWire is configured using routers to create a hierarchical point-to-point system with high speed parallel paths.

Implement SpaceWire in a convenient PCI-104 or PC104p format. With PC104p the four channels fit within the defined connector space. The SpaceWire specification calls for LVDS signaling, and a specific 9 pin micro-D connector. Connect the PC104p-SpaceWire to other SpaceWire compliant devices without electrical interface issues.

Four fully independent and highly programmable LVDS IO channels are provided by the PC104p-SpaceWire design. In the SpaceWire implementation the channels pass tokens between two independent state-machines to provide the proper protocol. The SpaceWire protocol is advanced with link testing, error handling, command and data protocols built in. The SpaceWire electrical interface is point-to-point. With the SpaceWire protocol, it is easy to build either a hierarchical architecture system with routers or a home-run wired system. Equipment can interact with any other node in the system. PC104p-SpaceWire provides a bridge from PC104p <=> SpaceWire. Channel based DMA offloads your CPU and increases performance in your system. Time Code support provides a complete solution. Please refer to the manuals at the bottom of this page for detailed information

SpaceWire features automatic link testing when a node is brought on line - released for operation via software. The transmitter sends NULLs until NULLs are received and then sends FCTs until FCTs are received. The initial frequency is specified [ECSS-E-ST-50-12C] to be 10 MHz. Once the auto link test has passed, the hardware can switch to the programmed rate. A local oscillator is used to supply the 10 MHz reference clock for initialization. A programmable PLL is used to support operation once the link is established. The PLL is programmed via software and is referenced to the oscillator. The PLL has 4 independent clocks tied to the four channels to allow for independent rate selection. The driver supports loading the PLL from the "JED " files used to program the PLL.

The SpaceWire protocol has flow control. The local memory on the PCI-SpaceWire will not overrun. In situations where the data being sent to the SpaceWire card is not buffered it is recommended to use a "-128" model with large FIFO´s on channel 0. The issue is upstream - if there is an unbuffered or under-buffered data source that will loose data if the link is throttled back the larger FIFO´s will help. The larger FIFO´s will provide more room to accumulate data if the system is not ready to allow the PC104p-SpaceWire to DMA transfer it immediately. The DMA transfers are higher bandwidth than the SpaceWire transfers allowing the system to catch-up once the DMA transfers restart. At 100 MHz and 80% data transfer the 128x32 FIFO will provide about 52 mS of data storage. The host would have to ignore the PC104p-SpaceWire interrupt requests for longer than 52 mS before throttling would occur. In most systems this is sufficient time to stay out of the throttled mode. To unload a full FIFO with DMA running it will take 128K/33M = .4mS => the unload to load multiplier is stongly in favor of the host side allowing the host to catch-up to the SpaceWire link once the delaying event has passed.

The interface is optimized to minimize the latency on the PCI bus. Using DMA the SpaceWire traffic is stored locally to "feed" the transmitter or store data from the receiver. The data across the link happens at the programmed rate. WIth DMA the data across the PCI bus happens at the max bandwidth of the bus with the FIFO´s providing the rate matching. Each channel has FIFO memory with 4 Kbytes TX and 4K bytes RX standard and up to 512K bytes as an option. The FIFOs are 32 bits wide to optimize data transfer from the PCI bus. The base FIFO´s are internal to the FPGA and utilize dual ported RAM configured as a FIFO. Two external positions are available for larger FIFO´s to be installed to support one of the channels in both directions or two of the channels in one direction.

The programmable FIFO flags are supported for interrupt driven or polled operation. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any debth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. For small messages, or command and control situations using the polled or interrupt driven modes makes sense. For larger transfers it is recommended to use the built in DMA path which self regulates the traffic eliminating the need for dealing with the interrupts other than the DMA completion interrupt. The DMA size can be much larger than the FIFO size to allow long "hands off" transfers. Your CPU can be busy with other processing instead of handling a lot of interrupts when DMA is used. The independent DMA per channel architecture makes this possible.

Dynamic Engineering Drivers are supplied with reference application software. The reference application software includes a complete test suite for the internal and external functions of the card and in some cases added features like board-to-board loop testing. The reference software is provided in source form so you can "copy and paste" into your application for a running start.

PMC-SpaceWire is supported with the DESWBO Dynamic Engineering SpaceWire BreakOut tool for debugging SpaceWire systems, cables, and the DESWCB Dynamic Engineering SpaceWire Connector Board which provides a SpaceWire Cable to system cable interface.

If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface. email us your wish list or call today!

PC104p-SpaceWire Block Diagram



The standard timing uses the data and strobe to transmit and to receive the data. The data is transmitted as a command or data. The strobe provides the transitions for clocking when the data is unchanged between adjacent bit times.

SpaceWire Standard Timing




PC104p-SpaceWire Features

  • Size
  • Standard dimension PC104p or PCI-104 card

  • Transmit Speeds
  • 10 MHz initial rate per SpaceWire Specification. Software selectable secondary rate for transmit channel. Max. frequency currently 180 Mhz. Oscillator and programmable PLL combined for user frequency support. Independent selection per channel.

  • PCI Speed
  • Standard 33 MHz. operation

  • PCI Access Width
  • Standard 32 bit operation supported.

  • Software Interface
  • PCI registers are read-writeable. Transmit and Receive functions separated. Channels separated for ease of use. Drivers are available for Windows®, Linux and VxWorks

  • Interrupts
  • Transmit and Receive state-machines, FIFO Programmable almost empty [transmit] and programmable almost full [receive] have programmable interrupts. Status can be polled for non-interrupt driven operation as well. End of DMA transfer.

  • Signaling
  • LVDS interface devices are utilized.

  • IO
  • The IO is available via the 9 Pin MDM connectors as specified in ECSS-E-ST-50-12C. The differential IO is properly routed with controlled impedance, and matched lengths on each of the pairs.

  • Interface
  • ECSS-E-ST-50-12C specification compliant. Time Code is supported.

  • Power
  • +5 and 3.3V. Other FPGA voltages converted with on-board regulators.

  • Memory
  • Separate FIFO´s are provided for TX and RX of each channel. Internal Block RAM creating 1K x 32 is standard for all channels. 128K x 32 is available on channel 0. Add -128 to part number for this option.

  • DIP switch
  • An 8 position switch is available to allow for configuration control, multiple Spacewire boards in a chassis and to facilitate integration



  • STEP
  • STEP files are available to support your system integration. Please contact sales@dyneng.com for this option.


    PC104p-SpaceWire Benefits

  • Speed
  • PC104p-SpaceWire is optimized for serial interfacing requirements. FIFO memories coupled with independent channel based DMA off-load the CPU. The FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the SpaceWire has independent and interconnected channel functions. All channels can operate at maximum rate in parallel.

  • Price
  • PC104p-SpaceWire is available off-the-shelf at a reasonable price. Custom versions can also be arranged. SpaceWire is easily programmed to implement new functions. Previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. A modified SpaceWire will represent a large cost and time savings in your budget.

  • Ease of Use
  • PC104p-SpaceWire is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and engineering kits help with integration into your system. Windows® Linux, and VxWorks® drivers available.

  • Availability
  • Dynamic Engineering works to keep the PC104p-SpaceWire in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with the std version then send updated FLASH later to help get your project going - right away.

  • Size
  • PC104p-SpaceWire is a standard PC104p or PCI-104 card and meets the mechanical specifications. PC104p- SpaceWire can be used in all PC104p slots.

  • PCI Compatibility
  • The PC104p SpaceWire is PCI compliant per the 2.3 specification.



    Ordering Information
    1 year warranty
    Quantity discounts available


    PC104p-SpaceWire-4Kb FIFO per channel, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Four channels. ISA connector installed. ISA connector is pass through only.

    PCI-104-SpaceWire-4Kb FIFO per channel, standard SpaceWire [ECSS-E-ST-50-12C] timing and protocol. Independent DMA channels and Timecode support. Four channels. This build version does not include the ISA connector.

    -128-add 512K [128K x 32] FIFO´s to channel 0 [TX and RX]

    -128RX-add 512K [128K x 32] FIFO´s to channel 0 and 1 RX


    -CC- Add Conformal Coating

    Select PC104p / PCI-104 Form Factor, Engineering Kit, Driver & Development Tool Options:


    Quantity

    Engineering Kits
    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. The Engineering Kits are standardized in description to help with selection. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    PC104p-SpaceWire-Eng .......... Integration Support Engineering Kit includes: Board level Schematics [PDF], and MDM-SpaceWire-Cable

    Software Support is included with your purchase. Current drivers are available for Windows [XP, 2000, etc. Win32 model, Windows7], VxWorks, and Linux kernel 3.0.0-17 [Ubuntu 11.10] 32 and 64 bit models [previous kernel versions also available.] Driver for
    TenAsys INtime real-time operating system also available. Please specify which driver package you need with your purchase order. All drivers come with a reference user application which includes loop-back testing, DMA use, PLL programming etc. Software and additional files provided with hardware purchase are intended for limited use only and are not intended for individual sale.



    Warning - Some i7 LGA1155 motherboards have PCI interrupt issues The link provides a list of chipsets that provide native PCI support and operate properly with SpaceWire and other high bandwidth applications.

    Manuals
    SpaceWire Hardware and Software Manuals are located on the SpaceWire Summay page, covering board level design descriptions, bit maps, pinouts, operation, driver installation, calls, and use.

    PC104p-SpaceWire Block Diagram with External FIFO Implemented


    Related Products

    MDM-Spacewire Cable
    : Lab Environment Spacewire Cable
    MDMSpacewire-Cable

    DESWCB
    SIngle cable to multiple MDM connector adapter. Order options for 1-28 MDM connectors


    DESWBO
    SpaceWire Monitoring tool for debugging your SpaceWire system. Test points and LEDs for status, traffic flow counts etc.


    Dynamic Engineering's Hardware and Software design overview


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