VPX2IP

  • Windows® or Linux driver included with purchase
  • Single PCIe lane operation ↣ can be installed in any VPX 3U slot.
  • 2 IndustryPack Module positions w/ 8⇆32 MHz. operation
  • Independent IP control buses with overlapped instruction execution
  • Fused, FIltered 5V, +12V, -12V supplied to IP´s
  • Multi-word accesses supported including 64, 32, 16, 8 bit and larger payload handling to IP´s
  • Full memory space supplied to each position
  • 3U size
  • Ribbon Cable Bezel Cutout
  • 1 year warranty standard. Extended warranty available.
  • Extended Temperature standard.
  • ROHS and Standard processing available


2 position VPX IP Carrier, VPX IP Adapter, VPX IndustryPack® carrier, VPX IndustryPack® Adapter for IP modules


IndustryPack® Modules are an important part of solutions for Embedded situations. Rugged, small, light .. just right for many applications. IndustryPack® Modules require a "carrier" in most cases to adapt them to the system. Dynamic Engineering has carrier solutions for a variety of formats. VPX2IP is designed to support VPX solutions. Alternate types available available for PC104p, cPCI, and PCI, PCIe and planned for cPCIexpress, PC104express.

VPX2IP is part of the IP Compatible family of modular I/O components. VPX2IP provides two IndustryPack® module sites in one 3U VPX slot. VPX2IP acts as an adapter, converter, carrier, and bridge between the PCIe bus and your IndustryPack® hardware.

VPX2IP is supported with Windows® compliant WDF drivers for Win7 and XP etc. as well as Linux support. Coming is VxWorks support. The drivers come with a generic IP driver to allow use with "unknown" IP´s <=> IP´s that do not have a driver designed yet. For example, third party IP´s.

IndustryPacks are 16 bit devices, and the PCIe bus supports larger payloads. VPX2IP accepts up to 128 byte payloads, and converts to word accesses. Most modern CPU´s can generate 8, 16, 32 and 64 bit instructions. The IP accesses can be auto-incremented or static address accesses. With the static access option the intended word can be accessed multiple times. With auto-incremented addresses multiple addresses are accessed. The strength of the PCIe bus is in handling larger payloads. VPX2IP provides the capability of handling larger payloads to reduce the average execution time. By changing from 16 bit accesses to 32 the overhead is cut in half and by going to quad instructions the over head is cut in 4 leading to much higher bandwidth. For payloads larger than 64 bits DMA is needed to create the packets. The current VPX2IP implementation includes the larger payload capabilty using external DMA. We are working on FPGA supported DMA to make CPU independent.

With Gen1 PCIe t takes about 2.5 uS to read a 16 bit value from a target device. With reads the data from the IP must be accessed, and a return payload constructed, and transferred to the host before the host can proceed to the next instruction. The access time for the IP Module is only 94 nS at 32 MHz with 1 wait state. The response time is dominated by the over head. This is based on a loop of 1000 accesses to a 32 MHz IP with 1 wait state in the memory space. [Performed on PCIe3IP] (2.451 uS was the tight loop average). The same loop with 32 bit accesses took an average of 2.556 uS or 1.278 uS per 16 bit read. The 64 bit loop provided 2.741 uS or .685 uS per 16 bit read. Larger payloads will approach the actual read time of the IP HW.

With writes the time is much lower due to the ability to auto respond before the write is completed, and the FIFO´s allowing storage of multiple commands per IP module. With the same parameters as the above and a write loop, the average for 16 bit access is .548 uS, for 32 bit .301us/word and for 64 bit .205uS/word. With larger transfers the access time will approach the IP access time on an average per word basis.

The Dynamic Engineering implementation does not require any special features on your IP module. Larger transfer sizes are especially useful for repetitive data transfers - loading or reading from RAM or FIFO´s faster will reduce the overhead on your CPU leading to more available time to process the data leading to lower cost or more capable systems.

Each position has a separate clock controller for 8 and 32 MHz operation. The frequency to be changed on the fly. The state-machine within the bridge design automatically locks to the IP Slot frequency as programmed.

Each PCIe transaction is pre-decoded and forwarded to separate IP Module handling logic. Each Module has separate memory and control interfaces to allow for overlapped IP operation. For example IP 0 can be executing a read or write in parallel with IP 1 and IP 2. Multiple commands can be stored for execution by each IP. Synchronization between the IP´s is available to provide multi IP sequenced programming should that be necessary.

VPX2IP asks for MSI interrupts during enumeration. If provided by the system, MSI interrupts will be available for operation. Legacy interrupts are provided when MSI interrupts are not programmed by the system.

Each IP position has "self healing" fused, filtered power. Each IP Module has separate bulk and bypass capacitance.

Industry standard 50 pin [ribbon cable] headers are used with the IO connectors. The connector at the bezel is a right angle condo model and is mounted through the bezel. The bezel connector is outfit with ejectors. Rear IO is an option. All of the IO is routed as differential pairs with matched length for each connector, controlled impedance and jumper resistors in place to minimize stubs. With the bezel IO option all IO are available from both positions. With rear IO there are 64 signal possibilities and 100 potential IO from the two IP modules. Additional resistor selections are provided to allow for a mix of IO from the two positions to be mapped to the rear VPX connector.

Ribbon cable or discrete wire cables can be interfaced directly with the VPX2IP. Alternatively the HDRterm50 can be used to create a terminal block interface.

The IP´s can be reset from the control register within the FPGA via the software interface. In addition at power-up the IP´s are provided the 200 mS reset as required by specification.

LED´s are provided to each of the IP slots for activity indicators. When each slot is accessed the LED is flashed. The FPGA provides a "one shot" circuit to stretch the "on" time to make it visible. Power indicator LED´s are provided using voltage monitors. An additional eight user LED´s are available for debugging or other purposes.

A surface mount "dip switch" is available for configuration control or debugging purposes. The switch values are available to be read via the PCIe bus. The switch is used for deterministic control by the driver. When multiple carriers are used in the same system the switch is used to allow the driver and application software to "know" which carrier maps to which handle. Further the slot information for a particular IP is stored to create a "vector" pointing to a specific slot on a specific carrier. Deterministic control of specific interfaces is easily achieved with this system without hardwiring system data into your software. The application software will be more portable and not break when new assets are added to the system (and your PCIe addresses change).

IP accesses are protected by a watch-dog timer. The timer is started at the beginning of each IP access. If the timer expires before the IP being accessed responds, a bus error internal to the VPX2IP is created. The VPX2IP responds normally to the host, not creating an errror on the PCIe bus, and provides status and an optional interrupt to alert the host to the problem with the IP. The Bus Error timer is useful in situations where the software may want to cause a bus error to find out what is installed or where a hung system would have consequences.

Connector positioning is compatible with IP-Debug-Bus will allow the user to isolate and debug the control interface of an IP. The IP-Debug-IO can be used in conjunction with the VPX2IP and IP-Debug-Bus to provide test-points on the IO signals and loop-back capability for the IP.

VPX2IP has an alternate "mini-map" option available. The standard design provides the full address space to the IP Memory space. The mini-map provides a minimized memory space equal to the ID, IO, and INT spaces with 128 bytes. The total PCIe memory space is reduced to 2K with this option. Please download the alternate manual to get the address map and other details. Please order with the -MM option for the mini-map.

VPX2IP is an extended temperature board. The extended or "Industrial Temp" version has components rated for -40C to +85C minimum. This temperature range will need to be derated based on your chassis thermal situation.

VPX2IP Features

  • Size
  • 3U aircooled VPX card.

  • IP compatible slots
  • 2 independent positions.

  • Clocks
  • Each position has independent selection of 8 and 32 MHz operation. Clock selection can be changed on-the-fly with glitch free operation.

  • Access Width
  • Each position can be accessed as byte, word, or multiple word payload [x32, x64 etc]. Multiple word accesses can be static or auto-incrementing to the IP slot.

  • Bus Error
  • The Watch-Dog timer protects against PCIe bus hangs by responding when the IP is not installed or has a failure.

  • Cable interface
  • Industry standard 50 pin box header connectors. Through the bezel or rear IO options.

  • Software Interface
  • Control registers are read-writeable
    IO, ID, MEM, INT spaces supported.
    Windows® and Linux Drivers available

  • Interrupts
  • Each IP has 2 potential interrupts. All are handled as MSI or Legacy types on the PCIe bus. Control registers are provided to enable amd tailor the pace at which interrupts are sent to the host and Status registers are provided to determine the source of the interrupt.

  • Power Requirement
  • +5V, +12V, -12V current determined by IP´s installed. 3.3V used by FPGA. +12V used to create -12V for IP´s, local DC:DC power supplies for efficient power conversion. Full IP spec power available to each position.

  • LED´s
  • monitored +1.2V, +3.3V, +5V, +12V, -12V, activity LED´s. 8 user LED´s also included.

  • DIP switch
  • An 8 position switch is available to allow for configuration control, or to facilitate debugging, and to provide a positive ID of each VPX2IP in your system

  • Reliability
  • estimated 1.3 million hours. Bellcore. GB 25c


    VPX2IP Benefits

  • Speed
  • With the direct PCIe to IP Bridge design featured in the VPX2IP the access to your hardware happens faster than in competing designs. The 32/64 bit access capabilities and overlapped IP access further extends the lead in speed. Compatible with mult-processor systems without sacrificing access times for single CPU systems. Multiple threads with accesses to different IP´s are supported.

  • Price
  • System level cost is best when reasonably priced reliable hardware is used and NRE minimized. With VPX2IP, driver support for the carrier and IP level, reference software, history of reliable operation, and fantastic client support your cost per unit and overall costs are attractive. Please check the current per item pricing with the storefront lower on this page. Orders can be placed via the on-line ordering system or via phone / email PO order systems.

  • Ease of Use
  • VPX2IP is easy to use. A point and shoot user interface to the IP sites. Please download the manuals and see for yourself. Reference software is provided in source form to get you started. The generic IP interface allows the driver to be used with IP´s without a driver specific to that design.

  • Availability
  • We expect VPX2IP to be a popular board. We will work to keep the VPX2IP in stock. Send in your order and in most cases have your hardware the next day. We can ship with FedEx pick-up everyday, and other carriers as requested.

  • Size
  • VPX2IP is a 3U VPX board which conforms to the VPX/PCIe mechanical and electrical specifications. Eliminate mechanical interference issues.

  • IP Compatibility
  • VPX2IP is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the VPX2IP. All other IP Modules which are compliant with the VITA specification can be expected to work. ID, IO, INT, and Memory spaces are supported in all positions. The -MM option reduces the overall PCIe address space requirement for those designs not using the full IP Memory space.

  • PCIe Compatibility
  • VPX2IP is a PCIe compliant device. VPX2IP can be expected to work in any PCIe compliant backplane using PCIe8LSwVPX3U


    Ordering Information
    VPX2IP
    options:
    VPX2IP Standard 2IP carrier - Industrial temperature components. Right angle header connector at Bezel position
    -ROHS Use ROHS processing. Standard processing is "leaded"
    -RIO Option to have a blank bezel without a cut-out. Rear IO is implemented via P2.
    -CC Option to add Conformal Coating




    VPX2IP Drivers..... Software Support VPX2IP Win7 or Linux compliant drivers:
    VPX2IP-XP/7 Windows®XP/7or Linux drivers for VPX2IP. The drivers are designed to be overlayed with individual IP Module(s) driver(s). IP drivers are auto installed for each instance detected. Please see the Driver manual for the specifics of writing your board interface. Please contact Dynamic Engineering if you would like us to produce one for your IP or a third party design. Our drivers come with IP-Generic which is automatically installed when a specific driver is not found for a particular IP Module. IP-Generic can be used to control your IP including handling interrupts, and accesses to all 4 space types.

    Linux
    The VPX2IP Linux driver is a bus driver capable of supporting multiple (up to 64) Industry Pack buses/carrier cards. This driver interfaces with the ipack-core Open Source code to support Industry Pack devices. This Open Source code has been slightly modified, and is included with the tar-ball for this driver.

    A generic IPACK driver (ipack_gen) and user library (libipack) has been developed by Dynamic Engineering. This driver and library may be sufficient for developing user space drivers for a device depending upon the complexity of that device. Other device specific user libraries and kernel drivers are available for Dynamic Engineering Industry Pack modules. The diagram below illustrates possible layering of Industry Pack components:


    Please contact Dynamic Engineering if you would like us to produce an IndustryPack specific driver for your IP or third party design.


    Manuals

    Click on the link to Download selected manuals in PDF format.
    Download the
    VPX2IP Hardware Manual
    Download the IP Carrier Windows®7 manual. For PCIe and PCI based carriers
    Download the VPX2IP Linux base Driver Manual
    Download the Library IndustryPack Linux Manual


    Related Products
    IP-DEBUG-IO II IP IO Connector Break-out Adapter
    IP-DEBUG-BUS IP module extender specialized for debugging
    HDRterm50 50 position terminal block with ribbon cable connector
    HDRribn50 Ribbon Cable for IP Modules with strain relief and cable pull tab
    IP-MTG-KIT Mounting Hardware for IP Modules


    Dynamic Engineering's Hardware and Software design overview


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