PCIe8LSwVPX3U

PCIe8LSwVPX3U is an 8 lane PCIe adapter with switch isolation for VPX development. The switch isolates the spread spectrum clocking found in most PC´s from the VPX port. PCIe 3.0 compliant, 1-8 lanes can be used by the installed VPX. Local power conversion for the 3.3V and 5V rails with efficient switching power supplies. Secondary power connector can be installed for high power consumption VPX cards. 15A on 3.3V and 5V rails max.[Rev 03 and later] Power monitoring circuits on the VPX and switch power rails. Status indicators for switch. Available now.

P0 on the VPX device mates with J0 on PCIe8LSwVPX3U. The connector is used for power, JTAG, and global addressing. A dip switch is supplied to allow user selection of the global address. The JTAG signals are are routed to a header on PCIe8LSwVPX3U. The 12V rail from the PCIe bus is used to generate the 3.3V and 5V supplied to P0.

The power supply designs utilize switching regulators controlling MOSFET´s. An LC filter insures clean power at the VPX device. The PCIe gold fingers are rated for 1.1A each, and a total of 5.5A on the +12V rail. 55W are available to the card after power conversion. Please note this is the combined power requirement across the +12, +5, and 3.3V power used by the VPX. In most cases 55W is sufficient. PCIe8LSwVPX3U has a standard PC Power Connector to allow additional 12V power to be added to the card. The two supplies are DIODE coupled. In some cases the 12V supply on the backplane will not be adequately routed by the PC causing voltage sag on the 12V. If this occurs use the cable connector to compensate. The power supplies include the bulk capacitance to properly bipass the FET´s and post conversion voltage rails. In addition the VPX connectors are bipassed with a 470 uF capacitor. The power supplies are checked with voltage monitor circuits. The LED´s are not illuminated unless the voltage is within the defined range.

The switch on PCIe8LSwVPX3U is interconnected with the PCIe lanes from the gold finger connections. Matched length, 100 ohm differential pair routing techniques are employed to allow for trouble free operation. Your PC can use spread spectrum clocking, and the built in switch isolates the spread spectrum upstream port from the down stream VPX side. New with Revision B, PCIe8LSwVPX3U supports both SSC and NSSC for the down steam port [VPX side]. With switch settings the clocking reference for the VPX interface can be updated to use a high precision 100 MHz independent clock or the REFCLK - 25 MHz with SSC.

We use the VPX8LXMC3U carrier to allow an XMC-Parallel-TTL to be installed onto the PCIe8LSwVPX3U via the adapter. The carrier can use REFCLK, or a local high precision reference to support the PCIe links. We use the rear IO from the XMC to test the path through to the SCSI connector at the bezel of PCIe8LSwVPX3U.

The Rear IO (P2) connector is carefuly routed to a 68 pin SCSI connector. 100 ohm differential routing with matched length traces. We recommend using our SCSI cable and the HDEterm68 breakout block with the SCSI connector.

Alignment pins are supplied to make sure of correct installation. The VPX installed will be perpendicular to the PCIe8LSwVPX3U with the component side to the right [relative to the photo above]. The VPX connector is located on the right hand side of the PCIe8LSwVPX3U in a position to allow a PCI or PCIe 1/2 length card to be used in the slot in front of the PCIe8LSwVPX3U.

LED´s are provided for 3 switch status signals. FATAL is provided to indicate a fault with the switch, PG0 and PG1 indicate the level of link activity on Port 0 and Port 1. A steady LED indicates PCIe 3.0 operation, flashing indicates PCIe 2.0 or PCIe 1.0 depending on the rate of flashing, and off indicates an unused port. Port 0 is the upstream port and in a new PC will likely show a steady LED for PCIe 3.0 operation. Port1 is the downstream port and after enumeration with the installed VPX will show the speed achieved on that port. The Switch allows for different upstream and downstream speeds. The switch has internal memory which will help with system traffic levels when connecting to a lower speed secondary port. Please see the manual for more information.