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IP-Pattern
TTL model with 32 bit Pattern Generator plus 16 bit GPIO Port
IP-Parallel-IO Description
- TTL model features 32 bit Pattern Generator and 16 GPIO
- Pattern Generator supports User Data
- Pattern Generator has pre-programmed wave shapes. User can program the limits, slope, frequency, duration.
- Rising and Falling Ramp, Pyramid and Inverted Pyramid, Square, Trapezoidal, Shift
- Windows and Linux Drivers available
- 1 year warranty standard. Extended warranty available.
- ROHS and Standard processing available
IP-Pattern Block Diagram
IP-Pattern will have several options to cover TTL, LVDS, RS-485 IO Types. IP-Parallel-TTL-PATT is built on the IP-Parallel-IO PCB. This model has 48 TTL IO. 32 are allocated to the Pattern Generator function with the remaining 16 utilized with a GPIO port featuring Change of State [COS] operation. Two of the GPIO bits can be programmed to provide an external trigger input and an external reference clock for the pattern generator output. IP-Parallel is available as an add-on IndustryPack Module for use with carriers on all of the common buses: VPX, VME, cPCI, PCI, PCIe, and PC104p.
The Pattern Generation portion of the design uses a 100 MHz reference clock with programmable divisor to control the update rate. The FIFO [see block diagram above] can be loaded with user patterns and broadcast - Type 0. Additional types are provided by the design to provide Rising and Falling Ramps, Pyramids and inverted Pyramids, Square Wave, Trapezoidal, and Shift Up. The Types are controlled by user parameters for the Start and Stop value, Slope, Horizontal Count [Trapezoids], and total count of waveform cycles to generate. Hardware checking is in place to allow Slopes that are not even divisibles of the Start-Stop defined range. Over and Under shoot can be simulated as well as clipping depending on the values chosen.
Since the User Mode has control over all of the IO it is possible to supply a file with a subset of the IO allocated to several outputs. For example, 4-8 bit generators can be supported with the merged file loaded to control the 4 groups of 8 bits. In addition, the square wave generator can be used to create up to 32 clocks in parallel with the rate controlled by the programmed divisor.
The GPIO section has 16 lines and each line can be set to be driven or not. All lines are separately inputs. The inputs can be programmed to capture Rising and/or Falling events to create interrupt requests or status as desired. Signals can be treated as edge dependent or levels. For level control the Polarity setting can be used to flip the sense of the line to integrate with your control scheme. The sampling rate for the COS engine is programmable.
The IP Module driver can be instantiated multiple times to control multiple cards by the same CPU. IP-Pattern when coupled with the Dynamic Driver "knows" what slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right card. The IP Driver can determine which type of IP-Parallel is installed and load the correct driver.
PCIe implementations are supported with the PCIe3IP and PCIe5IP.
Applications from 1 to 80 TTL GPIO lines and 1 - 5 Pattern Generators per PCIe slot.
PCI implementations are supported with the PCI3IP and PCI5IP.
Applications from 1 to 80 TTL GPIO lines and 1 - 5 Pattern Generators per PCI slot.
cPCI 3U is supported with the cPCI2IP. Applications from 1 to 32 TTL GPIO lines and 1 - 2 Pattern Generators
cPCI 6U is supported with the cPCI4IP. Applications from 1 to 64 TTL GPIO lines and 1 - 4 Pattern Generators.
PC104p is supported with the PC104pIP. Applications from 1 to 16 TTL GPIO lines and 1 Pattern Generator
PC104p situations with a custom mechanical can be done with the PC104p4IP.
Channel counts from 1 to 64 TTL GPIO Lines and 1 - 4 Pattern Generators per PC104 stack position.
IP-Pattern will have several options to cover TTL, LVDS, RS-485 IO Types. IP-Parallel-TTL-PATT is built on the IP-Parallel-IO PCB. This model has 48 TTL IO. 32 are allocated to the Pattern Generator function with the remaining 16 utilized with a GPIO port featuring Change of State [COS] operation. Two of the GPIO bits can be programmed to provide an external trigger input and an external reference clock for the pattern generator output. IP-Parallel is available as an add-on IndustryPack Module for use with carriers on all of the common buses: VPX, VME, cPCI, PCI, PCIe, and PC104p.
The Pattern Generation portion of the design uses a 100 MHz reference clock with programmable divisor to control the update rate. The FIFO [see block diagram above] can be loaded with user patterns and broadcast - Type 0. Additional types are provided by the design to provide Rising and Falling Ramps, Pyramids and inverted Pyramids, Square Wave, Trapezoidal, and Shift Up. The Types are controlled by user parameters for the Start and Stop value, Slope, Horizontal Count [Trapezoids], and total count of waveform cycles to generate. Hardware checking is in place to allow Slopes that are not even divisibles of the Start-Stop defined range. Over and Under shoot can be simulated as well as clipping depending on the values chosen.
Since the User Mode has control over all of the IO it is possible to supply a file with a subset of the IO allocated to several outputs. For example, 4-8 bit generators can be supported with the merged file loaded to control the 4 groups of 8 bits. In addition, the square wave generator can be used to create up to 32 clocks in parallel with the rate controlled by the programmed divisor.
The GPIO section has 16 lines and each line can be set to be driven or not. All lines are separately inputs. The inputs can be programmed to capture Rising and/or Falling events to create interrupt requests or status as desired. Signals can be treated as edge dependent or levels. For level control the Polarity setting can be used to flip the sense of the line to integrate with your control scheme. The sampling rate for the COS engine is programmable.
The IP Module driver can be instantiated multiple times to control multiple cards by the same CPU. IP-Pattern when coupled with the Dynamic Driver "knows" what slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right card. The IP Driver can determine which type of IP-Parallel is installed and load the correct driver.
PCIe implementations are supported with the PCIe3IP and PCIe5IP.
Applications from 1 to 80 TTL GPIO lines and 1 - 5 Pattern Generators per PCIe slot.
PCI implementations are supported with the PCI3IP and PCI5IP.
Applications from 1 to 80 TTL GPIO lines and 1 - 5 Pattern Generators per PCI slot.
cPCI 3U is supported with the cPCI2IP. Applications from 1 to 32 TTL GPIO lines and 1 - 2 Pattern Generators
cPCI 6U is supported with the cPCI4IP. Applications from 1 to 64 TTL GPIO lines and 1 - 4 Pattern Generators.
PC104p is supported with the PC104pIP. Applications from 1 to 16 TTL GPIO lines and 1 Pattern Generator
PC104p situations with a custom mechanical can be done with the PC104p4IP.
Channel counts from 1 to 64 TTL GPIO Lines and 1 - 4 Pattern Generators per PC104 stack position.
IP-Pattern Features
Size
1.8x3.9 inches nominal single slot IP Module. Type II with low profile devices on rear
IO
IP Module IO connector
Clocks
Compatible with 8 and 32 MHz IP bus operation. 50 MHz. Oscillator. 100 MHz. internal reference
IP Decoding
ID, IO, Mem and INT spaces supported.
Parallel Interface
48 independent TTL per module. Carrier determines number of modules that can be installed.
IO Configuration
32 allocated to Pattern Generator [31-0] and 16 to GPIO [47-32] Single ended with open drain 24mA drivers and 470 ohm pull-ups. 31-0 can be received.
Interface
Open drain drivers
Test
All IO can be set and read-back. FIFOs can be looped back. All registers are R/W other than Status. Built In Test [BIT] can be accomplished with a combination of loop-back tests.
Pull-up Resistor
470 standard, 1K, 4.7K available on TTL lines.
Interrupts
All GPIO can be programmed to cause interrupts. Each IO is programmable to be masked, active hi, active low, edge or level sensitive. Master enable for data channels. Interrupts are mapped to INTR0n on IP bus. Master enable can be disabled to allow polled operation.
Power Requirement
+5V. Approximately 52 mA at 5V typical unloaded.
SW Interface
All FPGA registers are read-write. All registers on word addresses. 32 bit registers on LW boundaries to allow 32 bit accesses on carriers that support this operation [All Dynamic Engineering carriers do].
Current Fab Number
10-2001-0104
Reliability
1.496 million hours GB 25C Bellcore MTBF
Custom
Approximately 55% utilized FPGA. Additional Types can be added to base design. Send in your suggestion.
IP-Pattern Benefits
Speed
The IP interface supports 32 MHz operation for quick data loading and unloading. The interface supports interrupts and polling. Dynamic Engineering carriers support 64 bit[PCIe models]/32 bit[PCI models] to 16 bit conversion in HW allowing for higher throughput and lower overhead. The built in functions can be used to offload the CPU from generating the patterns. When using the User Pattern mode, burst writes can be used to transfer data to the storage FIFO.
Price
System level cost is best when reasonably priced reliable hardware is used and NRE minimized. With IP-Pattern, driver support for the carrier and IP level, reference software, history of reliable operation, and fantastic client support your cost per unit and overall costs are attractive. IP-Pattern is inexpensive and can save money in other ways too.
Ease of Use
IP-Pattern is easy to use. Direct access to the registers. Set the frequency, Start, Stop and other parameters as needed. Please download the manuals and see for yourself. The engineering kit provides a good starting point for a new user. The User Application software and driver will get you up and running quickly. SIngle and multiple card capable. The driver has direct calls to read or set any of the IO lines. The example software includes loop-back testing. Interrupts are supported with the driver, and tested with the reference software.
Availability
The IP-Parallel-IO family including IP-Pattern are considered stocked items. With Dynamic Engineering´s in house manufacturing capability, if we are out of a particular model we can make more in short order.
IP Specification Compatibility
IP-Pattern is compliant per the VITA 4 - 1995 specification. Tested with PCI and PCIe based carriers. All Dynamic Engineering IP Modules are compatible with the PCIe3IP, PCIe5IP, VPXI2IP, PCI3IP, PCI5IP, cPCI2IP, cPCI4IP, PC104pIP etc. IP-Pattern will operate with any IP specification compliant carrier board.
Part Number: IP-Parallel-TTL-Patt
Ordering Options
-
Replace the "IO" with the following options:
- -ROHS Use ROHS processing. Standard processing is "leaded"
- -CC Option to add Conformal Coating
Base: 48 TTL IO with ports 31-0 allocated to Pattern Generator and 47-32 to GPIO
Add additional options to the "- number"
IP-Pattern Drivers
Software Support for IP-Pattern includes: Windows® reference SW package
The IP driver is layered and operates on top of the Carrier driver. IP drivers are auto installed for each instance detected. Please see the Driver manuals for the specifics of each type.
Drivers and Reference SW are developed for each type / version of IP-Pattern implemented. When custom versions are ordered the NRE will include providing Windows, Linux, and or VxWorks packages. For off-the-shelf models, select on the manuals tab, the Windows® and Linux SW shown is included with your purchase of the HW. A small one-time charge is required for the VxWorks versions. Unsupported SW versions may have an NRE requirement.
Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.
Reference diagam of how our Linux Driver / Application layer operate with the Carrier and IP Module.
The IP driver is layered and operates on top of the Carrier driver. IP drivers are auto installed for each instance detected. Please see the Driver manuals for the specifics of each type.
Drivers and Reference SW are developed for each type / version of IP-Pattern implemented. When custom versions are ordered the NRE will include providing Windows, Linux, and or VxWorks packages. For off-the-shelf models, select on the manuals tab, the Windows® and Linux SW shown is included with your purchase of the HW. A small one-time charge is required for the VxWorks versions. Unsupported SW versions may have an NRE requirement.
Integration support is available. Please contact Dynamic Engineering for this option or download the Technical Support Description from the Company button.
Reference diagam of how our Linux Driver / Application layer operate with the Carrier and IP Module.
IP-Pattern Manuals
Click on the links to Download selected manuals in PDF format.
IP Carrier and Module Quick Start guide for Windows®10
IP-Parallel-TTL-PATT HW Manual
IP-Parallel-TTL-PATT Driver Manual for Windows® 10/11
VxWorks IP Module Manual
IP Carrier Linux Manual
Linux IP Module Manual
IP Carrier and Module Quick Start guide for Windows®10
IP-Parallel-TTL-PATT HW Manual
IP-Parallel-TTL-PATT Driver Manual for Windows® 10/11
VxWorks IP Module Manual
IP Carrier Linux Manual
Linux IP Module Manual