cPCI Receiver Controller

cPCI Receiver Controller

cPCI Receiver Controller Simplified Block Diagram
This design is from 2008. The design has been migrated to the VPX platform with the latest version called VPX-GLIB. The intermediate version was called VPX-RCB. If your project requires cPCI or some of the unique features of this version we can bring the design forward to be manufacturable with current devices etc.

The cPCI Receiver Controller is a 3U 4HP design that can be used for many purposes. The primary design implementation is to act as the controller slice within a digital receiver. The host computer can access the Receiver Controller over the PCI bus within the cPCI system. The Receiver Controller buffers commands from the host and converts them to the appropriate format to interface with the rest of the Digital Receiver. The initial design is controlled with several SPI [Serial Peripheral Interface] buses.

The Receiver Synthesizer and Calibration Source interfaces have unusual 2 bit parallel SPI buses with programmable length [1-32 bits] operating at 20 MHz. The on board A/D uses an SPI bus to task and return data. The DAC uses an SPI bus to program the channel and value to output. An on-board temperature sensor is provided and it is accessed with a 5th SPI bus. The hardware takes care of storing the command, conversion, and interaction with the device. Status is provided to indicate when additional commands can be sent or when data is available.

Each of the SPI buses is controlled within the FPGA and separately buffered with 24 mA LVTTL line drivers. The FPGA logic is programmable to allow new definitions for each of the SPI buses or new buses altogether.

The ADC is implemented with an 8 channel device. The ADC is tasked with the SPI bus. The host selects the channel it wants to convert. The bus tasks the ADC with the channel number, and options for single ended or differential measurement, unipolar or bipolar encoding, and power options. When the conversion is completed the hardware reads the data back from the ADC and stores it into the FPGA to be read by the host CPU. A valid bit is set when the new data is stored. The channel pairs are routed for differential operation and can be used as single ended. The lower channels have a divider implemented to allow measurements above the 4.096V reference [18V]. The upper channels have options for open detection.

The DAC is implemented with an 8 channel device. Each channel has an inverting buffer. The output swings from 0V to minus 3V to control the attenuators within the receiver. Two are provided per channel connector. The DAC is tasked with the SPI bus. The host selects the channel it wants to convert. The bus tasks the ADC with the channel number and value to output. A valid bit is set when the new data is stored. Individual channels and groups of channels can be set in parallel.

Texas Instruments TMP123 is used to measure the local temperature on the surface of the board near the FPGA. The sensor is read with an SPI bus. A write to the port causes a conversion to take place. A read from the port retrieves the data - already converted and stored. Conversion status is provided. The temperature range is -40 to +125C. The measurements are within 2C, and within 1.5C for a reduced range of -25C to +85C.

The Digital Receiver requires several voltages. The cPCI backplane supplies 5V to the cPCI Receiver Controller. The 5V is converted to the local voltages required [1.2, 2.5, 3.3] and to +/-15, +24, -5 to support the other receiver functions. The power provided to the rest of the receiver is fuse protected with self-healing fuses. The alternate voltages are converted using efficient switching power supplies. Filtering is provided to on each rail to provide clean power.

A UART with differential IO is provided for serial communications. The UART is supported with deep FIFOs on TX and RX sides. [1023 x 8]. The parity and stop bits are programmable. The frequency is programmable. The baud rate is based on an 18.432 MHz reference provided by the on-board PLL and divided locally under SW control. All of the standard rates can be selected, and by changing the PLL reference custom ones can be attained. The transceivers are rated to 40 MHz. The RX side uses a 16x clock and could be programmed to operate at baud rates near 12.5 MHz.

Two SMA connectors are supplied with a 10 MHz clock reference. The signal is LVTTL. A mini-DB9 connector is supplied with 125 MHz LVDS for an additional reference clock. The initial reference for the 10 MHz and 125 Mhz can be from an external reference or from the local oscillator. In the case of the oscillator a 50 MHz signal is upconverted to 100 MHz. The 100 Mhz is used as a reference within the design to generate 20 MHz, 10 MHz, 2 MHz for the SPI buses. The 10 Mhz is muxed to be the internally generated version or the external version. The 10 MHz is then upconverted to create the 125 MHz. A dual counter is provided with control from SW to capture a known count with the internally generated 10 MHz and the external 10 MHz for comparison purposes - signal present and accuracy.

There are 24 LVTTL buffers, 7 RS-485 transceivers and 1 LVDS transceiver used within the Receiver Controller. The transceivers are programmable for direction. The transceivers are set to the directions required for the initial design and can be modified for other requirements. For example and external 125 MHz clock could be received by the LVDS buffer and brought into the design. Some of the LVTTL buffers are used in parallel making a total of 18 unique signals. One signal is buffered to all 6 of the communications connectors.

The universal PCI interface is 32/33 and can support DMA. The base design is register accessed.

The FPGA is a Xilinx Spartan 3 2000 with plenty of uncommitted gates to expand capabilities, and add new features. For example it is planned to add the FPGA CPU capability in the future. Most of the block RAM is available for new functions. Cables, Breakouts, and custom cables available. Detailed Hardware manual [PDF] available for download at the bottom of this page.