PCI-LVDS-8R

PCI-LVDS-8R was designed in 2001. This webpage is provided for reference purposes. If you like the concept and want to purchase we can update the design to be manufacturable with current parts etc. plus support for modern OS. We can also enhance the design to make use of the newer FPGAs and DDR. In addition, PCIe-AlteraCycloneIV is available with PCIe-Spartan-VI due for release. Please contact Dynamic Engineering for more information.

PCI-LVDS-8R is a PCI card with 8 channels. Each channel has memory, processing, and LVDS serialized input. The input is compatible with the TIA/EIA-644 LVDS standard. The serialized data is received with parallel serial data streams plus a reference clock. With the LVDS electrical standard long distances and quiet operation at high rates are possible. The TI interface device accepts the seralized LVDS signals and outputs a parallel word with reference clock. The parallel word can be up to 21 bits. Each group of 7 bits are deserialized independently using the common reference clock and down converted to the parallel word. The base model "8R" uses 14 of the 21 bits for the data and control. The "2R" model uses all 21 bits of the parallel interface.

The 8 channels are programmable with the ability to enable the channels of interest, the size of the memory allocated to each channel, the method of reception and the synchronization to each transmission. Each channel is supported with independent FIFO memory at strategic locations to allow full speed operation and the use of the banked SDRAM. Tags are inserted into the bitstream which are used to determine which data to trigger on and which to store. The amount of data to capture is programmable. The amount to skip can be programmed.

Once received the data is loaded into a channel FIFO for storage until the SDRAM can read in the new data. When the FIFO has data the SDRAM controller is alerted with a request to move the data. The flags are set to use burst data movement for efficient operation. Each channel has a separate FIFO. The channels are organized into two groups of 4. Each SDRAM controller arbitrates between the 4 requesting FIFO´s to move data into the SDRAM without allowng FIFO overruns.

The Latch Xlinx converts from 32 bit FIFO to 64 bit SDRAM data and down converts the reference rate to keep the pipeline balanced. Data is moved in Bursts whenever there is enough to move a complete page. Any LW coherent size can be moved with the hardware automatically making the necessary paging adjustments.

Once loaded into the SDRAM the data is available to the system to read using DMA transfers. The amount of memory per channel is programmable: the start address for each channel can be programmed as well as the length of the data to be received allowing all of the memory to be allocated to once channel or one quarter to each channel or whatever is required. For example in the "2T" model all of the memory for each bank is allocated to a single channel in each bank. In standard "8T" operation the channels are set-up in a symmetrical fashion.

A mode is available where the "8R" operation can be performed without using the SDRAM. It is called Direct mode. One channel of the 8 can be designated to read directly from the front end receiver FIFO directly to the DMA FIFO. The data is then directly moved to system memory. This mode is useful for real time monitoring of a channel.

The first customers for the 8R and 8T needed to use multiple cards within each chassis. Specifically 10 cards were placed into an expansion chassis providing 80 channels. The power consumption is not particularly high, and with 10 cards was too much for the 5V or the 3.3V rail of the power supply. The cards come with an option to operate using the 5V or the 3.3V power rail as the main source of power to allow multple boards to be used in the same chassis without overloading the power supply - it is recommended that you mix 5V and 3.3V cards when working with multiple cards. Please note that the PCi interface is "universal voltage", and not affected by the power rail option.

For more complete information please download the hardware manuals. Bit maps, diagrams, pinouts etc. are contained within.



PCI-LVDS-8R block Diagram



PCI-LVDS-8R Data Flow Diagram