IP-Tape

IP-Parallel-TTL Block Diagram



The IndustryPack compatible IP-Tape design adds 48 digital parallel IO lines to one slot of your carrier board. IP-Tape is a special version of the IP-Parallel-TTL design, and it is a member of the IP-Parallel-IO family. The IO is dedicated to a DTC interface. Other interfaces can be implemented. The DTC interface has 22 Address, 16 Data plus Parity, 4 control and 5 status lines. Parity is automatically generated in write mode and checked in read mode. Parity is programmable to be odd or even. Outputs in "tape" mode are driven with 24 mA open-drain devices. A 470 ohm pull-up resistor is provided on board. The registers are mapped as 16 bit words and are read-writeable.


IP-Tape IO Filter and Interrupt Control Block Diagram



All 48 IO channels can be used as interrupt generators. Interrupts are programmable to be enabled, active high or low, and edge or level triggered.

IP-Tape DTC Read Timing



The Timing can be altered with a change to the state-machine for other implementations. The state machine has counters to create the delays for each state. In this design, the counters are set to wait 4.5 uS after address is asserted to assert Address Enable [ENABLEn], then 1.5 uS before asserting Data Enable [DTC_ENA]. RW is asserted with ENABLEn. RW is high as a default and for read accesses. RW is asserted low for a write cycle. The Global enable [DTC_DECn] is asserted at the start of the cycle.


IP-Tape DTC Write Timing