PMC-BiSerial
PMC Compatible Bi-Directional Serial Data Interface




Please note that the PMC-BiSerial has been upgraded and the PMC-BiSerial-III is currently recommended for new designs

Two fully independent and highly programmable RS-485 / RS-422 IO channels are provided by the PMC-BiSerial design. The channels are supported by two independent state-machines created within the Xilinx FPGA. The transmit and receive protocol can be the same or different. Manchester encoding and decoding, standard serial [UART], control, command, instrumentation, and custom protocols can be implemented.

Each channel has a separate FIFO with 16Kb standard and up to 128Kb as an option. The FIFOs are 32 bits wide to optimize data transfer from the PCI bus. The interface is optimized to minimize the latency on the PCI bus. The data transfer size can be anything on the IO side. The FIFOs support internal loop-back testing. The loop-back test can be used for BIT and for software development. The Programmable Almost Full flag on the Receive FIFO and the Programmable Almost Empty flag on the Transmit FIFO are implemented to create an interrupt source. The programmable flags can be set to any debth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling.

The PMC-BiSerial has 20 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PMC-BiSerial. The transceivers support up to 12 Mhz clock and data rates.

The base design has a clock multiplexor coupled with a programmable divider to provide PCI, local oscillator and external clocking options along with divided versions. Custom oscillator frequencies can be installed when an exact frequency is required. The standard oscillator is 10 MHz.

If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

PMC-BiSerial Block Diagram



The standard timing [-IO] uses the clock and strobe to transmit and to receive the data. Data is shifted to the next bit on the falling edge and valid of the rising edge of the clock. The Set-up and hold are approximately 50/50 for a very stable interface. The clock edge can be reversed, the strobe can be made to be active high, the data width can be changed, the bit order can be changed etc.. Frequently parity or other error correction provisions are added. If the standard or one of the customer specific protocols will work for you - fantastic - and if not please let us know what you need and we can implement it for you.

PMC-BiSerial Standard Timing



PMC BiSerial Features

  • Size
  • Standard Single PMC

  • Transmit Speeds
  • Up to 12 MHz RS485 signaling supported. Designed in clock generator. Location for reference oscillator for specific frequency requirements.

  • PCI Speed
  • Standard 33 MHz. operation

  • PCI Access Width
  • Standard 32 bit operation supported.

  • Software Interface
  • PMC registers are read-writeable. Transmit and Receive functions separated.

  • Interrupts
  • Transmit and Receive state-machines, FIFO Programmable almost empty [transmit] and programmable almost full [receive] have programmable interrupts. Status can be polled for non-interrupt driven operation as well.

  • Signaling
  • 20 RS-485 / RS-422 compatible IO are provided. Any combination of transmit or receive channels can be created. Programmable termination.

  • IO
  • The IO is available via the PMC bezel connector and / or the PMC user IO connector Pn4.

  • Interface
  • The -IO version of the PMC BiSerial has support for Data, Clock and Strobe. Custom programmed interfaces are available with other options.

  • Power
  • +5 only. 3.3 converted with on-board regulator.

  • Memory
  • Separate FIFOs are provided for the RX and TX channels.
    4K x 32 is standard. 8K, 16K, and 32K x 32 are available.



    PMC BiSerial Benefits

  • Speed
  • The PMC BiSerial is optimized for serial interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. The FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the PMC BiSerial has independent transmit and receive functions. Both channels can operate at maximum rate in parallel.

  • Price
  • The PMC BiSerial is easily programmed to implement new functions. Many previously implemented custom designs are available too. Without the costs of schematic level design, layout, debugging etc. a modified BiSerial will represent a large cost savings in your budget.

  • Ease of Use
  • The PMC BiSerial is easy to use. Point and shoot - just fill the FIFO and set the start bit to get your custom protocol transmitting. Built in loop-back capabilities and engineering kits help with integration into your system. We can write a custom Windows® or Linux driver for you.

  • Availability
  • Dynamic Engineering works to keep the PMC BiSerial in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with the -IO version then send updated PROMs later to help get your project going - right away.

  • Size
  • The PMC BiSerial is a standard single width PMC card and meets the PMC mechanical specifications. The PMC BiSerial can be used in all PMC slots.

  • PMC Compatibility
  • The PMC BiSerial is PMC compliant per the IEEE 1386 specification.

  • PCI Compatibility
  • The PMC BiSerial is PCI compliant. You can develop with a PCI to PMC adapter - PCI2PMC or PCIBPMC.

    PMC-BiSerial Order Information

    1 year warranty
    Quantity discounts available

    PMC-BiSerial-IO - Standard version with 16Kb FIFO per channel, standard timing
    PMC-BiSerial-IO-8 - Standard version with 32Kb FIFO per channel, standard timing
    PMC-BiSerial-IO-16 - Standard version with 64Kb FIFO per channel, standard timing
    PMC-BiSerial-IO-32 - Standard version with 128Kb FIFO per channel, standard timing

    Engineering Kits

    PMC-BIS-ENG-1..........Engineering Kit for PMC-BiSerial includes: Board level Schematics [PDF], Reference Software [WIN NT, WinRT, Visual C ZIP file], HDEterm68-MP, HDEcabl68
    PMC-BIS-ENG-2..........Engineering Kit for PMC-BiSerial includes: PCI2PMC adapter card, board level Schematics [PDF], Reference Software [WIN NT, WinRT, Visual C ZIP file], HDEterm68-M, HDEcabl68


    Customer Special Versions
    You can order these too or request that we design one for you

    BiSerial version S-311
    Customer: Northrop Grumman
    Provide an interface to legacy radar systems using the S-311 protocol [data transfer between sub-systems within the radars]. WindowsNT® driver available for this version.

    PMC-BiSerial version BAE1
    Customer: BAE
    The BAE1 protocol implemented provides a 40 bit serially transmitted Real Time Clock programmable as a master or target. In target mode a local copy of the clock is kept for time-tagging local processes. When the master transmission is received the local clock is updated to stay in sync through-out the system. Industrial Temp.
    Windows® Driver Available

    PMC-BiSerial version BA1
    Customer: Boeing
    The BA1 protocol implemented provides a Serial Data Analyzer function used for network snooping in a test environment. -32 FIFO option.

    BiSerial version Nvy1
    Customer: Navy
    The Nvy1 protocol implemented provides Manchester encoded data inputs and outputs. -32 FIFO option

    BiSerial version PS1
    Customer: Photo Sonics
    Four Transmit and no Receive channels. 5 MHz transmit rate. 16K Fifo channel 0, 4 x 32 FIFO channels 1-3. Reference clock out. Reference strobe on channel 0. LSB first. Fixed synchronization pattern on channels 1-3. FIFO based synchronization pattern on channel 0.

    Related Products:

    HDEcabl68 SCSI II/III Cable, HDEterm68 SCSI II/III to 68 pin terminal block, PCI2PMC adapter card, PCIBPMC bridged PCI adapter card.


    Tar File/Driver(s): HSS.tgz Linux Tar File
    The attached zipped tar file contains a Linux Driver for the PMC Biserial IO. It contains the source code for the PMC BiSerial driver. This driver only does transmit. It is now well proven, operating for very long periods while generating continous data. The driver is able to be used with both the 2.2 and 2.4 series Linux kernels. It is an installable kernel module, it hasn't been set-up to be built into the kernel. Also included, is a test program that can be used to test the driver / card as well as serve as a skelton of an application. The Driver has been provided by one of our customers and is available for download in as-is condition. Please make use of the file, and if you make improvements - add a receive driver etc. please share; we would like to make that available too.

    The customer used the PMC-Biserial-IO with 16K FIFO option to continuously transmit data. The programmable FIFO level [Programmable Almost Empty] interrupt is used to control the data transfer to the PMC-BiSerial-IO insuring no gaps in their data stream.The PMC-Biserial-IO comes standard with 4K deep [x32] FIFOs and has options for 8K, 16K, and 32K debth. Depending on the OS ability to respond to interrupts, and the speed of transmission; different depths make sense for different applications. With Linux we recommend the 16K or 32K options.

    You must have Adobe Acrobat to read our PDF files.
    Hardware Manual:
    PMC-BiSerial manual PDF
    Hardware Manual: PMC-BiSerial-PS1 manual PDF
    Hardware Manual: PMC-BiSerial-BA1 manual PDF
    Hardware Manual: PMC-BiSerial-BAE1 manual PDF
    Driver Manual: pmcbis_bae1_wdm_man.pdf
    Hardware Manual: PMC-BiSerial-NVY1 manual PDF


    Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements



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