PMC-BiSerial III
PMC Compatible Multi Function Interface



The PMC BiSerial family has been updated to include a Spartan III [Xilinx] based card with expanded capabilities. Building on the knowledge and experience gathered from multiple IP and PMC BiSerial implementations and adding in the latest technology has created the PMC-BiSerial-III. The BiSerial III features completely isolated FIFO´s with 32 bit ports for increased adaptability and performance. The FIFO´s can be configured to support RX or TX or both directions. The [34] RS-485 / LVDS buffers have individual programmable termination, and direction controls allowing for any combination of "In´s and Out´s". Half-Duplex, Full-Duplex and uni-directional systems can be configured with software and VHDL. The denser, faster FPGA will implement the most complex state-machines.

The 34 IO can be configured to support one function, one function replicated several times, or multiple functions. For example the "RL1" has 8 UART channels, while the "ORB2" has 8 channels with 4 different functions. A real space saver when you need to have some Manchester to go with your UART and HDLC ports. A partial list of functions implemented in "Channels" includes: Manchester, Miller, SDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive. To support the functions the designs include: memory elements instantiated with FIFO, Dual Port RAM, register files, as well as state-machines, counters, timers, dividers, registers, CRC and Parity generation / checking, software drivers and applications, DMA [direct memory access] and the glue that goes with it. Our designs are all written in VHDL and done in a heirarchy allowing direct porting of different features to create new implementations.

PMC BiSerial III is recommended for new designs. More than 19 customerized versions of the PMC-BiSerial family and counting. The "ORB2" version has 8 channels with 4 different interfaces and multiple options on each interface. Ternary, Low Speed, Telemetry and High Speed interfaces plus a GPIO port. Mixed LVDS and 485 IO are used. DMA is supported on 3 of the types [6 ports] and register files on the Telemetry ports.

The hardware has been used to interface with a wide variety of equipment. What do you need to communicate with? Control? Capture data from? Please see the bottom of this page for descriptions and manuals for our customerized versions. We have been doing custom versions of the BiSerial since 1998 when the IP version first came out. We will be doing custom versions in the future with the next generation parts and features.

A new custom version can be implemented in a very reasonable time. Typically 1-2 weeks of design time for a medium sized project including the new VHDL set, Windows® driver, reference software package, and documentation. Examples of the designs performed to date are listed toward the bottom of this page. Click here or or scroll down to see if the configuration you need already exists or if we need to work on a custom version for you.

We can be rapid with our response because the designs are structured to allow channels to be moved in and out to create new design sets. Most designs have a fairly large component of reused "known good" VHDL that we can pull from allowing us to focus on the new functions required for your implementation. You are getting the benefit of many man-years of design and test time with each new version created. Join our high reliability clients by taking advantage of our know-how to help speed your project to completion.

If you need conduction cooling the ccPMC BiSerial III Trans is available. For PCIExpress we now have a native version with a DB37 connector. The PMC version can also be used along with a PCIe carrier when more IO is required. Please see the PCIeBiserialDb37.

PMC´s are mezzanine cards designed to be mounted to an adapter / carrier or host. Dynamic Engineering has PMC carriers for PCI, PCIexpress, cPCI, PC104p, VME and can do custom design´s specific to client requirements as well. Please use the handy JAVA pull-down menu at the top left of any page to navigate to other Dynamic Engineering products including carriers.

PMC´s are independently specificed through VITA for the form factor, connectors and pinouts of the PCI signaling; you can use the PMC BiSerial III design with any carrier from any vendor that supports standard PMC´s. To make it even easier the PMC BiSerial III has a universal PCI design to allow operation with VIO set to 3.3 or 5V.

It all starts with the PCB [Printed Circuit Board]. Quality design and quality materials are required to meet the strenuous requirements of many of our implementations. You can do the job quickly or you can do the design correctly. We pride ourselves on taking the time to put the extra work into our layouts. The quality goes in before the parts go on. In addition to routing strategy and layer counts, Via size, plating requirements, break-out trace widths, and materials are areas where quality comes into play. The via size and method of trace attachment to the via affect the signal shape and reliability. Using tear-drop trace connections to pads, via´s and through hole components enhance the reliability and minimize the impedance discontinuity resulting in a cleaner signal. Using 12 mil vias provides adequate copper for proper power distribution and more surface area to bond to where traces are interconnected. The combination provides better vibration endurance than smaller vias and traces would provide. The design has several power planes with sufficient copper weight and coverage to provide the references required for the routing plus the current and voltages needed by the various devices on the board. The larger features make the design work more difficult since there is less room to "play with" and the end result is worth it. PMC BiSerial III has an excellent track record for reliability.

The PCI interface has a published set of requirements for compliance which restrict length, impedance, loading and other factors. PMC-BiSerial-III is compliant with the PCI Specification. The IO section has requirements based on the IO type and the purpose for the IO. A very conservative approach has been taken to allow operation with any client requirement. The IO can be LVDS or RS-485. The IO on the connector side is differential with a 100 ohm impedance requirement. Between the FPGA and the tranceivers the IO is single ended. Each IO has separate direction, termination, and data lines to allow complete flexibilty. The design has matched length connections from the FPGA ball to the seating plane of the connector. The lengths are matched to the "mil". The Impedance is controlled and the signals routed with proper spacing to avoid cross talk etc. The other features including memory, PLL, oscillator, and power supplies are implemented within the PCB to exceed the operational requirements for those devices.

The Spartan III has internal block RAM which can be configured in a variety of ways. Currently, up to 48K x 32 of FIFO can be configured for internal channel memory support. In addition the memory can be configured as Dual Port RAM to allow direct addressing and retransmission of repeated patterns. The HW1 design has 32 channels each with 512 x 32 of Dual Port RAM.

Sometimes you just need more memory. Two external [to the FPGA] FIFO´s are available with 128Kx32 each. The FIFO´s are 32 bits wide to optimize data transfer from the PCI bus. Internal loop-back is supported. The loop-back test can be used for BIT and for software development. Programmable FIFO flags are supported on both sets of FIFO´s. Programmable Almost Full, Programmable Almost Empty, plus Full, Half Full, and Empty. The programmable flags can be set to any depth to allow the software a programmable delay from event to empty or full. The interrupts can be very useful when sending or receiving messages larger than the FIFO size. The interrupts are programmable and provisions are made to allow polling. In addition DMA can be programmed to fill or empty the FIFO with sizes larger than the FIFO size. The DMA will be hardware controlled to be held off when no data is available or no room is available. With the "Channelized DMA"™ capability and large FIFO´s the software application can have reduced interrupt counts to deal with while supporting larger and faster IO transfer rates.

PMC-BiSerial-III has 34 transceivers which can be used for any combination of input and output functions. Parallel and serial data, multiple channels, and different hand-shaking schemes can be implemented with the quantity of IO on the PMC-BiSerial. RS-485 transceivers support up to 40 Mhz clock and data rates. The LVDS transceivers are rated at better than 200 MHz.

The IO is available through either the front panel mounted SCSI III connector or Pn4 or some combination. Each transceiver pair is isolated from the connector with zero ohm resistor packs. The resistor packs are mounted front and rear and tied together at each pin to allow for a stub length of 1/16th in. The Connectors are routed from the resistor packs directly allowing for almost zero stub lengths and the option to connect front or rear IO options. In addition the IO have resistor packs tied between the IO and a power plane. The plane is strappable to allow 5V or GND on either rail. The IO can be set to provide a high or a low condition when not driven to support half duplex operation without adding resistors to your cables.

Clock options are frequently a major factor in embedded designs. Getting the right reference to the right part of the design and allowing for local control of exact frequencies. The PMC BiSerial III has a PLL with 4 programmable outputs, reference oscillator, internal DCM´s and buffering plus programable dividers instantiated within the VHDL. The PLL can be programmed to "any" fixed frequency, the DCM used to create phase variations, and local dividers to allow on-the-fly channel based frequency changes.

"Channelized DMA"™ is an important feature of the PMC-BiSerial-III design. With "Channelized DMA"™ you have a separate DMA engine for each transmitter and each receiver within each channel. Each state-machine can be serviced independently with DMA without requiring intervention from the host. Large data transfers can happen between multiple connections while the CPU is off doing something else. In non-channelized designs the CPU will have to intervene each time a different port needs to be serviced. With a channelized approach the hardware takes care of the local arbitration, and eliminates the intervention for better system performance and less latency.

If your situation demands a custom application we will update the Xilinx FPGA and IO components. Send us your timing and we will send you the interface. Please refer to the bottom of this page for previously completed "customerized" PMC BiSerial III implementations.
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PMC-BiSerial III Example Block Diagram

PMC BiSerial III ORB2 version block diagram
See the bottom of Dynamic Data Sheet for more options



PMC-BiSerial-III Features

  • Interface Types
  • Custom programmed interfaces are available. Please send us a timing diagram, and we can program one for you. Most interfaces can be adapted from our large library of designs within 1-2 weeks including the updated VHDL, Windows Driver, reference manuals etc. We can support on-site [ours] integration to help you get your application level software working.

    Alternatively choose one of the already completed versions and purchase off-the-shelf. Common requested and implemented interface types include: Manchester, Miller, SDLC, UART, Serial, Parallel, GPIO, COS, Custom, LADEE, NMS, Camera, Ternary, Low Speed, High Speed, Telemetry, Master & Target interactive IO, Adaptive

  • Signaling
  • 34 RS-485 / RS-422 / LVDS compatible IO are provided. Any combination of transmit or receive channels can be created. LVDS and RS-485 can be mixed. RS-485 bandwidth is lower when mixed [16 Mbps]. Programmable termination. Pull-up and Pull-down option on IO to allow controlled level when tri-stated. Option for marking or low state.

  • IO
  • The IO is available via the PMC bezel connector and / or the PMC "user IO" connector Pn4. The differential IO is properly routed with impedance control, pitch, and space plus matched lengths across all of the pairs. 0 ohm resistor packs are used to isolate the front and rear panel IO to allow single port designs to remove the bus stub to the removed port. Please specify if you do not want rear or front panel IO. Please note that the lower 32 channels [only] are routed to Pn4 due to pin limitations.

  • Transmit Speeds and Clocking
  • Up to 40 MHz RS485, and up to 200 MHz LVDS signaling supported. 4 channel software programmable PLL. Reference oscillator. Counters / Dividers / DCM for local clock control.

  • PCI Speed
  • PCI 33 MHz. operation Standard Target accesses, and "Channelized DMA"™ supported. "Channelized DMA"™ is a full DMA capability on each function in a multi-function implementation. Standard 32 bit operation supported.

  • Software Interface
  • PMC registers are read-writeable. Linux and Windows® drivers available. Design help for alternate OS implementations.

  • DIP Switch
  • An 8 bit "DIP Switch" is provided for user purposes. The DIP switch can be used to allow the application software to positively identify a PMC BiSerial III in a multi-board implementation. The PCI bus enumerates the address which means the application software can´t rely on the address to always match up with a particular card. With the DIP switch the particular BiSerial can be identified and postive control over a particular asset provided. Could be important depending on what you are connected to. The switch can also be used for software control, a debugging aide or other user purposes.

  • Interrupts
  • Software programmable interrupts on status, errors, completion of transfer, DMA, FIFO levels, custom events. Status can be polled for non-interrupt driven operation as well.

  • Memory
  • Separate FIFO´s / Dual Port RAM are provided for all channels. Internal FPGA Block RAM memory modules for fast access. Optional discrete FIFO´s -128K x 32 are available.

  • FPGA
  • Xilinx Spartan III 1500, 2000 and 4000 models are installed based on client requirements. FLASH is used to program the FPGA. In many cases any feature updates can be sent to your facility to reprogram without down time.

  • Power
  • +5 only. 3.3V, 2.5V and 1.2V converted with on-board power supply.

  • Temperature
  • Commercial Temperature is standard. Industrial [-40 <=> +85] is available.

  • Assembly
  • Standard [leaded] processing or ROHS compliant processing are available. See ordering options.

  • Conformal Coating
  • Conformal Coating is available to support operation in condensing environments.

  • Size
  • Standard Single PMC

  • Statement of Volatility
  • Download PDF here


    PMC BiSerial III Benefits

  • Speed
  • PMC-BiSerial-III is optimized for differential interfacing requirements. The FIFO memories and programmable interrupts off-load the CPU from most of the management other implementations require. FIFO access is optimized for the PCI bus further reducing overhead by speeding up the data transfer. On the IO side the PMC BiSerial has independent channel functions. Channels can operate at maximum rate in parallel. With the Spartan III "Channelized DMA"™ can be implemented and still have plenty of gates left for your application.

  • Price
  • PMC BiSerial is easily programmed to implement new functions. Many previously implemented "custom designs" are available too. Without the costs of schematic level design, layout, debugging etc. a modified PMC-BiSerial-III will represent a large cost savings in your budget. With our large and growing VHDL library your function(s) may be close to complete when we start since we can modify existing implementations or repackage them as required.

  • Ease of Use
  • PMC-BiSerial-III is easy to use. The registers are designed to be R/W without layering or other indirect control methods. Use the Dynamic Driver with Windows® or Linux or create your own. The HW manual has the full address and bit maps plus definitions for each function. In most cases the interfaces are "Point and shoot" - just fill the FIFO and set the start bit to get your custom protocol transmitting. The driver and user application reference software have built in utilities for parsing new PLL frequency files, loading the PLL, reading the switch, doing loop-back using DMA via the IO and between FIFO´s. Built in loop-back capabilities and engineering kits help with integration into your system. We can write a custom Windows® or Linux driver for you.

  • Availability
  • Dynamic Engineering works to keep the PMC BiSerial III in stock. Send in your order and in most cases have your hardware the next day. With a custom design a 1-2 week design period is usually required. We can support immediately with the another version then send updated FLASH Files later to help get your project going - right away.

  • Size
  • The PMC BiSerial III is a standard single wide PMC card and meets the PMC mechanical specifications. The PMC BiSerial III can be used in all PMC slots.

  • PMC Compatibility
  • The PMC BiSerial is PMC compliant per the IEEE 1386 specification.

  • PCI Compatibility
  • The PMC BiSerial is PCI compliant. You can develop with a PCI to PMC adapter - PCI2PMC or PCIBPMC. Use the Java pull-down menu´s for more carrier options.



    Engineering Kits
    General Descriptions: The SW options are shown with each model below. The reference software included in the User Application is provided in source form and is a complete project including calls to the driver to perform card functions, board identification from the system, a simple and powerful test menu etc. The driver is provided as .SYS and .INF files for Windows® and source for Linux.

    PMC-BIS-III-ENG-1
    Engineering Kit for PMC-BiSerial-III includes: Board level Schematics [PDF], Reference Software [WIN XP/2000 Driver Visual C ZIP file and or Linux Tar file], HDEterm68-MP, HDEcabl68

    PMC-BIS-III-ENG-2
    Engineering Kit for PMC-BiSerial III includes: PCI2PMC adapter card, board level Schematics [PDF], Reference Software WIN XP/2000 Driver Visual C ZIP file], HDEterm68-M, HDEcabl68

    Customer Special Versions & Manuals
    You can order these too or request that we design one for you

    PMC BiSerial III version BA19

    Customer: Boeing
    The BA19 implements a Master and a Target interface. Each interface has 8Kx32 FIFO and a dedicated DMA engine. The IO is LVDS, 8 bit parallel Data with Ready, Sync, and Clock. Ready and Clock are used to provide flow control. PLL is programed for rate control. The applications software works with the driver to capture data and store to HDD using DMA.
    Download the
    BA19 Hardware manual
    Download the BA19 Windows® Driver manual


    PMC BiSerial III version BA23

    Customer: Boeing
    The BA23 protocol implemented provides eight UART I/O channels each consisting of RS-485 transmit and receive data. The UART interface uses a 16x clock to detect received data bits. For channels 0-5 the interface can operate at up to 10.4 Mbits/second and uses byte oriented data. Each UART channel has separate Dual Port RAM to allow for retransmit of data. Multiple trigger and operational modes supported. The uper channels 6 and 7 have a 32 bit UART and are supported with FIFO memory. DMA and target access for all channels. Please download the HW manual for the details. This version is a variant of the BAE9 design with the upper channels modified for new funtionality.
    Download the BA23 Hardware manual


    PMC BiSerial III version BAE9

    Customer: BAE
    The BAE9 protocol implemented provides eight UART I/O channels each consisting of RS-485 transmit and receive data. The UART interface uses a 16x clock to detect received data bits. The interface can operate at up to 10.4 Mbits/second. DMA is supported for each channel independently. Each UART channel has separate Dual Port RAM to allow for retransmit of data. Multiple trigger and operational modes supported. Please download the HW manual for the details.
    Download the
    BAE9 Hardware manual
    Download the BAE9 Windows® Driver manual for IOCTL based Win7 and Win32 model drivers
    Download the BAE9 manual for High Performance Linux Driver


    PMC BiSerial III version HW1
    Customer: The Goebel Company
    The HW1 protocol implemented provides 32 Manchester encoded data channels per card. Each channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 channels.
    Download the HW1 Hardware manual
    Download the HW1 Windows® manual

    PMC BiSerial III version HW2
    Customer: The Goebel Company
    The HW2 version implements 8 channels of the HW1 protocol, plus 24 blocks of Asynchronous or SDLC IO. The SDLC takes 4 blocks per channel and the Asynchronous takes two. Each HW1 channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the 32 blocks. The SDLC channels are programmable for frequency using the PLL. The Asynchronous channels are designed with a UART style protocol. Please see the hardware manual for the details. Revision G or later design shipped unless ordered with -RevF appended to name.
    Download the HW2 Hardware manual - RevF FLASH
    Download the HW2 Hardware manual - RevG FLASH and later
    Download the HW2 Windows® manual
    Download the HW2 Linux; manual

    PMC Biserial III version LM5
    Customer : Lockheed Martin
    8 channels of half duplex serial interface. Each serial interface channel is supported with clock, strobe, and two data bits. With a 40 MHz serial clock 80 MHz data is effectively transmitted. Each channel is supported with memory in the form of a 1K x 32 FIFO to store transmit data or received data. Each channel is independent and can be programmed to be a transmitter or receiver. The IO is supported with LVDS devices and can be implemented with RS-485 as an option. Programmable interrupts, status bits, and r/w registers make up the programming interface.

    Download the LM5 Hardware manual

    PMC Biserial III version LM6
    Customer : Lockheed Martin
    The protocol implemented provides four I/O channels each consisting of LVDS transmit and receive data and clock. The on-board PLL is used to generate the two clocks required for the design. The PLL is programmable, and uses a 40 MHz reference oscillator to generate a wide range of frequencies. The target rates for this design are 10 Mbits/sec for channels zero and one and 62.5 Mbits/sec for channels two and three.

    Data for all channels is received MSB first using start and stop bits to separate data words. Channels zero and one send and receive 36-bit words (packets) consisting of two start bits (1´s) a 32-bit data field a parity bit and one stop bit (0) with data changing on the falling edge of the clock (stable on the rising edge). The parity bit is calculated using even parity over the data field. A data frame is terminated with an idle packet consisting of a 36-bit word of all 0´s. When no data is being sent, the data line remains in a 0 state.

    Channels two and three use different formats for transmitted and received data. A transmit packet consists of one start bit (1), a 32-bit data field, an odd parity bit and one stop bit (0) for a total of 35 bits. The received data-word is 66 bits long consisting of one start bit (1), a 64-bit data field and one stop bit (1). Each data-frame begins with a sync word in the upper-half of the first data word. If this is not seen, data will still be stored, but a framing error will be latched. Parity is not used on this interface. Both interfaces have data changing on the rising edge of the clock (stable on the falling edge).
    Download the LM6 Hardware manual
    Download the Windows® Driver manual

    PMC BiSerial III version MDS1
    Customer: MDS Aero - Canada
    The MDS1 protocol implemented provides 4 channel Manchester encoded serial interface. Each channel can operate with a selectable frequency, RX or Tx mode, unidirectional or bidirectional. CRC, Manchester, Ready_Busy, and other status provided. Internal Dual Port RAM blocks [512 x 32] used for each of the channels.
    Download the MDS1 manual
    Download the MDS1 Linux driver manual

    PMC BiSerial III version NASA1
    NASA1 is a 4 channel implementation with interfaces for three types of telemetry plus UART and Parallel Ports.
    Channel 0 provides the "LADEE - LLST" interface supported with DMA and 8Kx32 of FIFO in each direction. PLLA is used to set the TX reference frequency typically 40 Mhz. The interface is LVDS.
    Channel 1 provides the "NMS" interface supported with DMA and 8Kx32 of FIFO in each direction. PLLB is used to set the TX reference frequency typically 1-10 Mhz. The interface is RS-422 / RS-485.
    Channel 2 provides the "UART" interface supported with DMA and 1Kx32 of FIFO in each direction. PLLC is used to set the reference frequency typically 14.7456 Mhz. which is further divided within the channel to provide all of the standard baud rates. The interface is RS-422 / RS-485.
    Channel 3 provides the " Uplink and Downlink" interface supported with DMA and 1Kx32 of FIFO in each direction. Manchester encoded. PLLD is used to set the reference frequency typically 8 Mhz. which is further divided within the channel to provide the 8x and 2x clocks used for the Downlink and Uplink respectively. The rates are divided separately allowing for asymmetrical operation. The interface is RS-422 / RS-485.
    The remaining IO are used for a 14 bit parallel port with bit level direction control. RS-422/ RS-485 IO.

    Download the NASA1 Hardware manual
    Download the NASA1 Windows® driver manual

    PMC BiSerial III version NG8
    Customer: Northrop Grumman
    The NG8 design features 2 channels with transmit or receive "camera protocol". Each channel has Clock, HREF, VREF, BadPixel, and Pixel data [11-0]. "Channelized DMA"™ is used along with 133K x 32 FIFO to provide continuous operation. The transmit rate is selected with a PLL allowing for custom user frequencies. The image size is programmable. Blanking and active image areas are programmable. Interrupts, status and error checking. RS-485 is used for the IO.

    Download the NG8 Hardware manual
    Download the NG8 Windows® driver manual

    PMC BiSerial III version ORB2
    Customer: Orbital
    The ORB2 design features multiple protocols: 2 channels each of Ternary, LS, HS, and Telemetry data. Each channel can operate with a selectable frequency, Rx or Tx mode, status provided. Internal FIFO is provided 4Kx32 for Rx or Tx on the Ternary and LS ports. A combination of internal 4K x 32 and external 128Kx32 are provided on the HS ports. Programmable lengths and delays between packets sent. Programmable polarity on clocks, and strobes. Programmable bit order. Programmable frequency. Interrupts, status and error checking. RS-485 is used for the Ternary, LS and Telemetry ports. LVDS is used for the HS ports.

    Download the
    ORB2 Hardware manual
    Download the ORB2 Windows® driver manual

    PMC BiSerial III version OSEH
    Customer: restricted
    The OSEH protocol implemented provides a single transmit and receive channel each consisting of an RS-485 clock and data. The transmitter can use either an external clock reference, or an internal clock reference supplied by the on-board PLL.

    Download the OSEH Hardware manual
    Download the OSEH Driver manual

    PMC BiSerial III version RL1

    Customer: restricted
    The RL1 protocol implemented provides eight UART I/O channels each consisting of RS-485 transmit and receive data. The UART interface uses a 16x clock to detect received data bits. The interface can operate at up to 10 Mbits/second using a 160 MHz clock. DMA is supported for each channel independently. Each UART channel has 1K x 32 FIFO for transmit and another 1Kx32 for receive.

    Download the
    RL1 Hardware manual
    Download the RL1 Windows® Driver manual

    PMC BiSerial III version UART

    Customer: Applied Dynamics
    Current implementation has eight UART I/O channels each consisting of RS-485 transmit and receive data. The UART interface uses a 16x clock to detect received data bits. Received data is filtered with the 32 MHz. reference clock to remove line glitches. The interface can operate at up to 2 Mbits/second using a 32 MHz clock. Each UART channel has 255 x 32 FIFO for transmit and another 255x32 for receive in addition to Packet Definition FIFO´s. 3 modes can be selected per fully independent node: Standard UART (unpacked), Packed, and Packetized. In Packed mode 32 bit data is assumed allowing 4 characters to be read/written at a time. Packetized mode allows for non LW data lengths, and retains most of the efficiency of LW packing. Odd lengths [non LW boundaries] are loaded with the complete LW´s first then the remainder. The Packet length FIFO is programmed with the length to send. The Packet lengths can be loaded to transmit with minimal HW delay between Packets or with a programmed delay.

    Download the PMC BiSerial III UART Hardware manual

    PMC BiSerial III version SDLC

    Customer: Boeing
    8 Channels of full duplex SDLC [Synchronous Data Link Control] with internal or external clock reference. Software / PLL rate programability. Separate Tx and Rx 4K byte Dual Port RAM circular buffers. Interrupts [programmable] available for end of each message frame transmitted, at the end of all message frames transmitted, at the end of each received message frame, when an abort character is received. Masked status is available to allow operation in polled mode. I2O interrupts are also available. Please note: SDLC is a subset of HDLC and can be used in HDLC systems using byte delineated data. Linux and Windows driver/UserApplication support.

    Download the PMC SDLC Hardware manual
    Download the PMC SDLC Win7 manual
    Download the PMC SLDLC Linux Driver manual


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