IndustryPack Compatible Bi-Directional Serial Data Interface

The serial Input and Output channels are highly programmable and fully independent. The standard interface offers Ready, Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. RS422/485 and TTL compatability will interface to a variety of systems. If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

IP-BiSerial-ENG..........Engineering Kit for IP-Xilinx includes Board level Schematics [PDF], Reference Software [PCI3IP, WIN NT, WinRT, Visual C environment - ZIP file], IP-DEBUG-BUS, IP-DEBUG-IO. Purchase this kit once to support IP-BiSerial and other IndustryPack development. Each kit includes software specific to your choice of IP's.

Customer Special -RTN2 Version
You can order these too, or request that we design one for you

Customer: Raytheon
Data is sent and received lsb first using the rising edge of the clock to change data and the falling edge of the clock to capture data. The Strobe is asserted 1/2 clock before the first valid data clock and held 1/2 clock after the last valid data bit. Data, clock, and strobe are generated. The user reference clock is also used for the RX data in clock.

The receive section processes incomming data. Programmable parity can be tested to be odd, even and on or off. Parity errors are captured and held in a status register. The data is composed of 16 bit words with the optional parity bit creating a 16 or 17 bit length. The data is continuous using the strobe to indicate the start and end of the transmission. In addition to parity checking, frame, over-run, and word count errors are checked. Data can be received in a message of any number of words. The base FIFO size is 8K words. Longer messages can be received with the use of the Programmable Almost Full flag. The flag can be polled or used to generate an interrupt. When the FIFO is almost full but not full the software can read data out of the FIFO creating space for a longer message. An end of message interrupt is also available.

The transmit section creates the outgoing data. Data is stored into the 8K word transmit FIFO. The transmitter is enabled and the message sent. The message length is determined by the data within the TX FIFO. Long messages - beyond 8K words - can be sent with the Programmable Almost Empty flag used for an indication of when to load more data into the FIFO. Interrupts from the PAE and end of transmission are available. The data rate is programmable with a 12 bit counter providing multiple frequency options. The counter is referenced to the IP clock, an oscillator or a differential user clock. All options are user programmable.

Two user bits are provided - one transmit and one receive.

Timing diagram available in the manual. PDF link to the manual at the bottom of this page.

Block Diagram

Timing Diagram

You must have Adobe Acrobat read our PDF files.

IP-BiSerial-RTN2 Rev A manual PDF.

Try before you buy program

Back to IndustryPack compatible
Custom, IP, PMC, PC*MIP, PCI, VME Hardware, Software designed to your requirements

Home | News | Search the Dynamic Engineering Site

[an error occurred while processing this directive]