IP-BiSerial-Q1
IndustryPack Compatible Bi-Directional Serial Data Interface



Please refer to the IP-BiSerial-IO page for the base card description. IP-BiSerial-IO

The standard interface offers Ready, Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. RS422/485 and TTL compatability will interface to a variety of systems. If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

The Q1 version of the IP-BiSerial-IO is designated IP-BiSerial-Q1. The -Q1 has a custom Xilinx implementation which allows the user to control the mode of operation [16 bit or 32 bit], type of parity, and frequency. The received data is tested for parity and over-run errors. The interface has a programmable off state determination to provide for synchronization.

IP-BiSerial-ENG-1..........Engineering Kit includes Board level Schematics [PDF], Reference Software [PCI3IP, WIN NT, WinRT, Visual C environment - ZIP file], IP-DEBUG-BUS, IP-DEBUG-IO. Purchase this kit once to support IP-BiSerial and other IndustryPack development. Ask about our -3 and -5 kits which include a PCI carrier.

Customer Special -Q1 Version
You can order these too or request that we design one for you

IP-BiSerial-Q1
Customer: QinetiQ
The Q1 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP Clock is used to derive the reference clocks for serial operation. A range of frequencies is available; 62.5 KHz. is the base design frequency. Bursted clock and data. signals control data flow. 16 bit data with parity. LSB first, parity last. Single or double word transmissions. Parity and Over-run checked on the receive channel. Parity generated on the transmit channel. Programmable 16/32 bit operation and continuous mode. Multiple interrupt options. 1K x 16 FIFO buffers.

A range of frequencies is available; 62.5 KHz. is the base design frequency and is supported with the IP clock divided down. A programmable divider is provided to support other frequencies. For more details please download the manual.

The data is transmitted in 16 bit data packets with parity appended. The mode16_32 control bit for the transmitter determines if one or two of the 17 bit packets is sent at a time. If two are sent the transfer is done without a gap between the words. The LSB is transmitted first, parity last. The receiver section uses a seperate mode16_32 control to determine whether to load 16 or 32 bit data. In addition the receiver can be programmed to capture one data set and stop or to continuously capture data. At the end of transmission, or when the programmed number of words is received interrupts can be generated. The Programmable Almost Full Flag and Programmable Almost Empty Flag interrupts can be used with the Receiver and Transmitter to support long transfers.

The receive channel checks for Parity, and Over-run errors. Parity is generated on the transmit channel. Parity is programmable Odd and Even. The over-run error occurs if the Receive FIFO is full when it is time to write data to that port.

The Q1 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The FIFO can be written with IO or Mem space accesses. With a carrier supporting 32 bit conversion the FIFOs can be loaded and unloaded at 32 MHz using 32 bit data transfers. See the PCI3IP and PCI5IP.

The IP-BiSerial-Q1 has Windows®XP/2000 and Linux drivers available to support your integration effort. The driver works with the PCI3IP, PCI5IP, cPCI2IP and other compatible IP carriers.



You must have Adobe Acrobat 4.x to read our PDF files.

IP-BiSerial-Q1 Rev A manual PDF
IP-BiSerial-Q1 XP/2000 driver interface manual PDF
IP-BiSerial-Q1 Linux driver interface manual PDF


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