IP-BiSerial-NG2
IndustryPack Compatible Bi-Directional Serial Data Interface



Please refer to the IP-BiSerial-IO page for the base card description. IP-BiSerial-IO

The standard interface offers Ready, Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. RS422/485 and TTL compatability will interface to a variety of systems. If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

The NG2 version of the IP-BiSerial-IO is designated IP-BiSerial-NG2. The -NG2 has a custom Xilinx implementation which allows the user to control the width of the syncronization pulse, the time delay after the sync and the start of data, and the time between data words. The word transfer has an associated Word Sync signal to provide for framing and error checking. The Frame sync signal provides for message level synchronization. In addition to the programmable delays, the base frequency is also programmable.

IP-BiSerial-ENG-1..........Engineering Kit includes Board level Schematics [PDF], Reference Software [PCI3IP, WIN NT, WinRT, Visual C environment - ZIP file], IP-DEBUG-BUS, IP-DEBUG-IO. Purchase this kit once to support IP-BiSerial and other IndustryPack development. Ask about our -3 and -5 kits which include a PCI carrier.

Customer Special -NG2 Version
You can order these too or request that we design one for you

IP-BiSerial-NG2
Customer: Northrop Grumman
Frame and Word sync plus the synchronous clock control data flow. T1, T2, and T3 are programmable: Frame asserted, Frame to Word, and the inter-word gap. The delays are based on the transmitter reference rate.

A range of frequencies is available; 512KHz. is the base design frequency and is supported with an on-board oscillator [4.096 MHz]. A programmable divider is provided to support other frequencies. Programmable active edge of clock.. For more details please download the manual.

The data is transmitted in 32 bit data packets with parity appended. The MSB is transmitted first, parity last. Programmable received word count. The transmitter sends data until the FIFO is emptied for "any length" messages. At the end of transmission, or when the programmed number of words is received interrupts can be generated. The Programmable Almost Full Flag and Programmable Almost Empty Flag interrupts can be used with the Receiver and Transmitter to support long transfers.

The receive channel checks for Parity, Frame, and Over-run errors. Parity is generated on the transmit channel. Parity is programmable Odd and Even. The Frame detector checks the Frame and Word sync signals to determine if the channel has lost synchronization. The error is asserted if sync is lost. The over-run error occurs if the Receive FIFO is full when it is time to write data to that port.

The NG2 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The FIFO can be written with IO or Mem space accesses. With a carrier supporting 32 bit conversion the FIFOs can be loaded and unloaded at 32 MHz using 32 bit data transfers. See the PCI3IP and PCI5IP.



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IP-BiSerial-NG2 Rev A manual PDF.


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