IP-BiSerial-Miller IndustryPack Compatible Bi-Directional Serial Data Interface
Please refer to the IP-BiSerial-IO page for the base card description. IP-BiSerial-IO
The standard interface offers Ready, Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. RS422/485 and TTL compatability will interface to a variety of systems. If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!
The Miller version of the IP-BiSerial-IO is designated IP-BiSerial-Miller or IP-BiSerial-MLR. The -MLR has a custom Xilinx implementation which allows the user to encode data for transmission with "Miller" or to decode a received data stream. Miller encoding is a method of representing clock and data together in one data stream with an average of 50% duty cycle. The Miller technique is useful in all data transfer applications and especially so where balanced data is important - telemetry and fiber applications for example.
IP-BiSerial-MLR-ENG..........Engineering Kit includes Board level Schematics [PDF], Reference Software [WinRT or XP], IP-DEBUG-BUS, IP-DEBUG-IO. Purchase this kit once to support IP-BiSerial and other IndustryPack development. Ask about our -3 and -5 kits which include a PCI carrier.
Definition of Miller Code (also called Delay Modulation; DMM)
1. Miller Code is a method of encoding serial data.
2. All encoded information is contained in the spacing between transitions; the polarity does not matter.
3. The only permitted spacings between transitions are 1.0, 1.5, and 2.0 bit periods.
4. An input of ONE always produces a transition at the end of the bit period.
5. An inpit of ZERO produces a transition in the middle of the bit period unless there was a transition at the start of the period. Thus, a ZERO bit following a ONE bit never produces a transition.
Miller Code Rules:
1. Determine the time, T, between the last two transitions in units of the bit period.
2. The decoding may depend upon the last decoded bit so this must be remembered.
3. Start the decoding when a two bit period spacing (T=2) is found. Then the last bit is a ONE.
4. If T=1, the next bit is the same as the last bit.
5. If T=2, the next two bits are ZERO followed by ONE.
6. If T=1.5, AND the last bit = ZERO, then the next bit = ONE.
7. If T=1.5, AND the last bit = ONE, then the next two bits are ZERO and ZERO.
The IP-BiSerial-MLR has a Windows®XP/2000 driver available to support your integration effort. The driver works with the PCI3IP, PCI5IP, cPCI2IP and other compatible IP carriers. The -MLR IP driver requires the corresponding carrier driver.