IP-BiSerial-Miller
IndustryPack Compatible Bi-Directional Serial Data Interface



Please refer to the IP-BiSerial-IO page for the base card description. IP-BiSerial-IO

The standard interface offers Ready, Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. RS422/485 and TTL compatability will interface to a variety of systems. If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

The Miller version of the IP-BiSerial-IO is designated IP-BiSerial-Miller or IP-BiSerial-MLR. The -MLR has a custom Xilinx implementation which allows the user to encode data for transmission with "Miller" or to decode a received data stream. Miller encoding is a method of representing clock and data together in one data stream with an average of 50% duty cycle. The Miller technique is useful in all data transfer applications and especially so where balanced data is important - telemetry and fiber applications for example.

IP-BiSerial-MLR-ENG..........Engineering Kit includes Board level Schematics [PDF], Reference Software [WinRT or XP], IP-DEBUG-BUS, IP-DEBUG-IO. Purchase this kit once to support IP-BiSerial and other IndustryPack development. Ask about our -3 and -5 kits which include a PCI carrier.

Customer Special -MLR Version
You can order these too or request that we design one for you

IP-BiSerial-MLR
Customer: Nakano Science and Engineering

The Miller version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP or reference oscillator is used to derive the reference clocks for serial operation. An initial synchronization pattern is used with the receiver. The "sync" pattern can be used on a programmable word count to make sure sync is maintained. Multiple interrupt options. 8K x 16 FIFO buffers. 8 and 32 MHz IP clock rate operation. Encoding and Decoding of Miller data. TTL or 422 operation.

A range of frequencies is available; 128 KHz. is the base design frequency and is supported with the reference oscillator clock divided down. A programmable divider is provided to support other frequencies. The receive data stream uses a 10x clock to determine where the transitions are and what the data value is. The transmit rate is derived from the selected 10x clock. For more details please download the manual.

Initial bit sync is achieved by measuring the transitions until a 2T transition case is found. The data is known to be "01". The 2T period is used for initial bit sync because it is the only case where [in Miller coding] the current data does not depend on the previous data. Once the initial data is found the rest of the bits following can be decoded on-the-fly. The data is read in and passed through a 32 bit shift register. When the data matches the programmed sync patten the first data is captured and the counters initialized to capture the next word [32 bits] ,and to track the number of words captured for sync checking. A frame error is detected if the sync pattern is not detected at the programmed word count. The error is captured into the status register. The FIFO is tested as each word is written and if already full an Over-run error is generated.

The data is transmitted in 32 bit MSB first data packets continuously. The first data word can be the sync pattern if the leading bit of the sync pattern is '0'. If the MSB is a '1' then the first word needs to be some other data pattern to achieve bit sync ahead of the sync pattern being detected. The data is transmitted continuously until the FIFO is empty. When the FIFO becomes empty the transmit interrupt can be generated. If patterns longer than the 8K words are to be transmitted then the PAE flag can be used to generate an interrupt before the FIFO becomes empty and/or larger FIFO´s can be installed.

The MLR version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The FIFO can be written with IO or Mem space accesses. With a carrier supporting 32 bit conversion the FIFO´s can be loaded and unloaded at 32 MHz using 32 bit data transfers. See the
PCI3IP and PCI5IP.



Definition of Miller Code (also called Delay Modulation; DMM)
1. Miller Code is a method of encoding serial data.
2. All encoded information is contained in the spacing between transitions; the polarity does not matter.
3. The only permitted spacings between transitions are 1.0, 1.5, and 2.0 bit periods.
4. An input of ONE always produces a transition at the end of the bit period.
5. An inpit of ZERO produces a transition in the middle of the bit period unless there was a transition at the start of the period. Thus, a ZERO bit following a ONE bit never produces a transition.

Miller Code Rules:
1. Determine the time, T, between the last two transitions in units of the bit period.
2. The decoding may depend upon the last decoded bit so this must be remembered.
3. Start the decoding when a two bit period spacing (T=2) is found. Then the last bit is a ONE.
4. If T=1, the next bit is the same as the last bit.
5. If T=2, the next two bits are ZERO followed by ONE.
6. If T=1.5, AND the last bit = ZERO, then the next bit = ONE.
7. If T=1.5, AND the last bit = ONE, then the next two bits are ZERO and ZERO.

The IP-BiSerial-MLR has a Windows®XP/2000 driver available to support your integration effort. The driver works with the PCI3IP, PCI5IP, cPCI2IP and other compatible IP carriers. The -MLR IP driver requires the corresponding carrier driver.

You must have Adobe Acrobat 4.x to read our PDF files.

IP-BiSerial-MLR Rev A manual PDF
IP-BiSerial-MLR XP/2000 driver interface manual PDF


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