The serial Input and Output channels are highly programmable and fully independent. The standard interface offers Ready, Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. RS422/485 and TTL compatability will interface to a variety of systems. If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface....
IP-BiSerial-LM1 IndustryPack Compatible Bi-Directional Serial Data Interface
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IP-BiSerial-ENG..........Engineering Kit includes Board level Schematics [PDF], Reference Software [PCI3IP, WIN NT, WinRT, Visual C environment - ZIP file], IP-DEBUG-BUS, IP-DEBUG-IO. Purchase this kit once to support IP-BiSerial and other IndustryPack development
Customer Special -LM1 Version
You can order these too or request that we design one for you
Customer: Lockheed Martin Space Systems
Multiple fixed message lengths - program the number of bytes to be transmitted in a 16 bit register. Typical receivers, ACU's etc. require 48, 56 or 64 bit messages which are supported along with other lengths by the -LM1 design.
A range of frequencies is available; 10, 8, 4, 2,1 MHz and other frequencies can be derived from the IP clock, built in 10 MHz oscillator, or an external reference. For more details please download the manual.
The data is transmitted in data packets of programmable length. The length can be set to any size from 1 byte to 65K bytes. If the length programmed is larger than the storage FIFO then the data will have to be written during the transmission. The PAE [Programmable Almost Empty] interrupt will support the longer messages. For messages which will fit within the FIFO an automatic start feature is provided. When the data is written into the FIFO via the Memory Space the address is compared with the end of message address and when the addresses match the transmission is automatically started. This feature is handy for control interfaces with short lengths; for example when interfacing to a 56 bit receiver a 20% savings is realized by having the auto-start feature.
Data is read from the FIFO MS word first and sent MS Bit first. Bytes are appended until the terminal length is achieved.
A counter keeps track of the received data. The counter can be read to determine how many words are present in the FIFO to support the read data function. A second message can be received even if the first is not read [assumming there is space in the FIFO]. If a new count is written to the holding register before the previous one is read then an error [MC] bit is set to alert the user. The error does not affect the receiver action, it just means that the software will have to use the FIFO flags to support the read function. For longer messages the PAF [Programmable Almost Full] interrupt can be used - when the FIFO is almost full an interrupt is generated and a known amount of data can be read out. For short known length messages the data count can be used as an error check to make sure it matches the expected amount.
The LM1 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The FIFO can be written with IO or Mem space accesses. With a carrier supporting 32 bit conversion the FIFOs can be loaded and unloaded at 32 MHz using 32 bit data transfers. See the PCI3IP and PCI5IP.
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IP-BiSerial-LM1 Rev A manual PDF
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