IP-BiSerial-HDP
IndustryPack Compatible Bi-Directional Serial Data Interface



If your situation demands a custom application then we will update the Xilinx FPGA. Send us your timing and we will send you the interface.... email us your wish list or call today!

IP-BiSerial-ENG..........Engineering Kit for IP-Xilinx includes Board level Schematics [PDF], Reference Software [PCI3IP, WIN NT, WinRT, Visual C environment - ZIP file], IP-DEBUG-BUS, IP-DEBUG-IO. Purchase this kit once to support IP-BiSerial and other IndustryPack development

Customer Special -HDP Version
You can order these too or request that we design one for you

IP-BiSerial-HDP
Customer: US Navy
The HDP version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP Clock is used to derive the reference clocks for serial operation. A range of frequencies is available; 100 KHz. is the base design frequency. Bursted clock and data. signals control data flow. 16 bit data with parity. LSB first, parity last. Transmit and interrogate modes. Programmable delay between words. Parity and Over-run checked on the receive channel. Parity generated on the transmit channel. Multiple interrupt options. 1K x 16 FIFO buffers. Engineering kit available.


HDP Write only Timing Diagram


HDP Write with Read Timing Diagram

You must have Adobe Acrobat to read our PDF files.

IP-BiSerial-HDP Rev C manual PDF.


Try before you buy program

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