IP-BiSerial-IO
IndustryPack Compatible Bi-Directional Serial Data Interface





The serial Input and Output channels are highly programmable and fully independent. The standard interface offers Data, Clock and Strobe. The programmable output rates and a user oscillator position allow for flexible frequency selection. The adaptable interface allows for bursted or continuous operation, and all kinds of data / handshake protocols. For example - Manchester encoding, full and half duplex operation, synchronous and asynchronous data transfer. RS422/485 and TTL compatability will interface to a variety of systems.

If your situation demands a custom application then we will update the Xilinx FPGA. Now with more than 17 versions. Our customers have the IP-Biserial in use for a wide variety of applications including: Simulation of expensive system components for test and control, robotics, telemetry, data capture and transfer, communications, translation between incompatible equipment types, signal generation, and control. What will you use the BiSerial for? Send us your timing and we will send you the interface.... email us your wish list or call today!

The evidence is in: the IP-BiSerial can handle most customer requirements. If your requirements are the exception please look at the IP-OctalSerial. The Octal version of the BiSerial has more FIFO [x4] more IO [24 vs 9] and more gates [Spartan II vs Spartan]. The IP-BiSerial is a cost effective solution for most situations, and the IP-OctalSerial is the solution for the more challenging designs or space constrained situations.


IP-BiSerial-IO Standard Timing



The IP Module driver can be instantiated multiple times to control multiple cards by the same CPU. IP-BiSerial when coupled with the Dynamic Driver "knows" what slot it is in and which carrier it is installed into. The slot and carrier information is required when using multiple cards in a PCI system with dynamic address assignment. A known system configuration can be combined with the slot and carrier information to deterministically access the right card

PCI implementations can be done with the PCI3IP and PCI5IP. Applications from 1 to 5 BiSerials per PCI slot.
cPCI 3U is supported with the cPCI2IP. Applications with 1 or 2 BiSerials per 3U cPCI slot.
cPCI 6U is supported with the cPCI4IP. Applications from 1 to 4 BiSerials per 6U cPCI slot.
PC104p is supported with the PC104pIP. Applications with 1 BiSerials per PC104 stack position.
PC104p situations with a custom mechanical can be done with the PC104p4IP.
Applications from 1 to 4 BiSerials per PC104 stack position.
3U VME is supported with the VME2IP. Applications with 1 or 2 BiSerials per 3U VME slot.
6U VME is supported with the VME4IP. Applications from 1 to 4 BiSerials per 6U VME slot.


IP-BiSerial Features

  • Size
  • single slot Type 1 IP Module.

  • IO
  • 9 RS485/RS422 transceivers. 10 std. / 40 MHz max. Resistor SIP termination.

  • Speed
  • 8 and 32 MHz IP bus operation. Up to 10/40 MHz on IO.

  • IP decoding
  • ID, IO, Mem and INT spaces supported

  • Memory
  • 2 FIFOs are supplied - one per channel. The FIFOs are designed to support independent operation on each channel. 2K per channel standard, other densities available up to 64K per channel.

  • Clocks
  • Internally generated and externally supplied clocks are supported with source selection and programmable divider. Standard rates: 8,4,2,1 MHz., 500, 250, 125, 64.5, 32.25 KHz. Customer versions have other options.

  • Access Width
  • all addresses are on 16 bit boundaries

  • ID PROM
  • Each version of the IP-BiSerial has a unique ID PROM for identification.

  • Write cycle to TX FIFO
  • Write cycles to the FIFO are supported with a write through buffer.

  • Write cycle to RX FIFO
  • Write cycles to the RX FIFO are supported for loop-back testing.

  • Software Interface
  • All registers are read-write. All registers on word addresses. Each channel as separate control registers.

  • Interrupts
  • Programmable interrupts for each channel are supported. Masked interrupts can be used in polled mode by reading the status register. Interrupts are mapped to INTR0n on IP bus.

  • Power Requirement
  • +5V

  • Oscillator
  • Provision for a local oscillator to generate custom frequencies.

  • MTBF
  • 3.12 million hours Bellcore SR332 MTBF


    IP-BiSerial Benefits

  • Speed
  • The transmit memory can be loaded quickly. 32 bit accesses are supported by loading from the memory space. Data write through is supported. Reading from the RX FIFO has also been optimized to support high speed operation. 32 and 8 MHz IP clock rates are supported. The Xilinx can handle high speed serial or parallel protocols. The IO are rated at 10/40 Mhz.

  • Price
  • Cost effective with options of FIFO density, IO speed, and quantity for optimized price and performance.

  • Ease of Use
  • BiSerial is easy to use. All registers are read-write and word aligned. There is a lot of felxibility with interrupt and polled mode operations. Please download the manual and see for yourself. The engineering kit provides a good starting point for a new user. The reference software does a loop-back test and set-ups the different modes of operation.

  • Availability
  • IP-BiSerial is still available in limited quantities. Please select IP-BiSerial-VI for any new implementations.

  • Size
  • IP-BiSerial in standard configuration is a Type 1 size IP module which conforms to the IndustryPack mechanical and electrical specifications. No Components on the rear means no mechanical interference issues. The IP-BiSerial can be used in all IP slots.

  • IP Compatibility
  • IP-BiSerial is IP compliant per the VITA 4 - 1995 specification. All Dynamic Engineering IP Modules are compatible with the PCI3IP and PCI5IP. The IP-BiSerial will operate with any IP specification compliant carrier board.


    Ordering Information
    IP-BiSerial-IO
    IP-Xilinx


    Related Products
    IP-DeBug-IO
    IP-Debug-Bus
    HDRterm50
    IP-MTG-KIT (Mounting Hardware)
    Quantity discounts available

    Engineering Kits
    Dynamic Engineering provides Engineering Kits to help our customers have a successful and quick integration. Engineering Kits will save time and money with decreased T&I. We recognize that different customers have different needs. The Engineering Kits are standardized in description to help with selection. The kits are segmented to allow for customers who only need hardware support, software support or a mixture. The Engineering Kit is highly recommended for first time buyers. The kit pricing is discounted to encourage their use.

    IP-BIS-Eng-1
    Base Engineering Kit for IP-BiSerial includes Board level Schematics for IP-BiSerial [PDF], IP-DEBUG-BUS, IP-DEBUG-IO.

    IP-BIS-Eng-3
    Base Engineering Kit Plus PCI3IP Carrier for IP-BiSerial includes Board level Schematics for IP-BiSerial [PDF], PCI3IP carrier, PCI3IP Windows® driver, IP-DEBUG-BUS, IP-DEBUG-IO.
    Please note that the PCI3IP driver includes the ability to work with specific drivers for all Dynamic Engineering IP´s and a generic driver to work with IP´s without a specific driver.

    IP-BIS-Eng-5
    Base Engineering Kit Plus PCI5IP Carrier for IP-BiSerial includes Board level Schematics for IP-BiSerial [PDF], PCI5IP carrier, PCI5IP Windows® driver, IP-DEBUG-BUS, IP-DEBUG-IO.
    Please note that the PCI5IP driver includes the ability to work with specific drivers for all Dynamic Engineering IP´s and a generic driver to work with IP´s without a specific driver.


    IP-Xilinx
    Order IP-Xilinx if you want to do your own development. A stock IP-Biserial board will be shipped with a blank PROM for the Xilinx. Purchase the IP-Xilinx-Kit to support your efforts. The standard Xilinx device is a spartan30-4 - plenty of room for your custom project.

    IP-Xilinx-Kit
    Engineering Kit for IP-Xilinx includes Board level Schematics for IP-Xilinx [PDF], IP-DEBUG-BUS, IP-DEBUG-IO, Xilinx IP bus interface design files in VHDL format. Purchase this kit once to support IP-Xilinx development. Options for this kit include ordering an IP Carrier and IP Carrier driver. The generic function within the driver can be used for your development of your unique IP.

    Customer Special Versions
    You can order these too or request that we design one for you

    BiSerial version BA1
    Customer: Boeing
    Intergrated Transmit and Receive channels. Odd or Even Parity generation and checking. Frame, Parity and overrun error checking on input channel. Transitions on the falling edge, valid data on the rising edge. Can be programmed to use an internal reference clock at multiple frequencies or the external reference clock.

    BiSerial version BA2
    Customer: Boeing
    Symetrical Transmit and Receive channels. Data, Clk, and Strobe. Odd or Even Parity generation and checking. Frame, Parity and overrun error checking on input channel. Transitions on the rising edge, valid data on the falling edge. Can be programmed to use an internal reference clock at multiple frequencies or the external reference clock. Input clock detection circuitry automatically switches to an internal reference when the clock is lost. Status is provided. Timing diagrams available in the manual.

    BiSerial version BA3
    Customer: Boeing
    The BA3 version of the BiSerial board has asymetrical transmitter and receiver functions. The transmitter sends data MSB first and uses a strobe the same width as the transmitter data. Data transitions on the rising edge and can be captured on the falling edge of the free-running clock. The transmit timing can be synchronized to the synchronization pulse that is provided. The sync pulse has a period of 2500 uS and a width of 4 uS. Timing diagrams available in the manual.

    BiSerial version BA4
    Customer: Boeing
    The BA4 version of the BiSerial board is used to capture manchester encoded data and to retransmit that data in "uart" compatable form. Unusual design with only the IDPROM implemented on the IP Bus. Manchester data is tested to find the first word of a block then stored into an internal FIFO. The stored data is re-ordered to be lsb first and modified with start and stop bits to create a data stream suitable for UART reception.

    BiSerial version BA5
    Customer: Boeing
    The BA5 version of the BiSerial board is used to receive data in UART form 1 start, 1 stop, 8 data, 1 parity. The received data is checked for parity, checksum, number of bytes, valid ID, valid count. Transmission of stored message in response to received message with status added from received message. 1 MHz clock reference input, bi-directional data.

    BiSerial version BA13
    Customer: Boeing
    The BA13 version of the BiSerial design is based on the Q1. The data and clock are low between transfers. The transmitter and receiver can be programmed to send 16 or 32 bit data. The transmitter and receiver can be programmed to generate and check parity or not. The parity, if used, is programmable; odd and even. The received data is checked for parity, and over-flow. Programmable transmit rate. Rising edge true data. 8 and 32 MHz IP clock compatible. 2K FIFOs.


    BiSerial version HDP
    Customer: USN
    The HDP version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP Clock is used to derive the reference clocks for serial operation. A range of frequencies is available; 100 KHz. is the base design frequency. Bursted clock and data. signals control data flow. 16 bit data with parity. LSB first, parity last. Transmit and interrogate modes. Programmable delay between words. Parity and Over-run checked on the receive channel. Parity generated on the transmit channel. Multiple interrupt options. 1K x 16 FIFO buffers. Engineering kit available.


    BiSerial version LM1
    Customer: Lockheed Martin
    Programmable message length 1-65K bytes. Data, clock and Strobe interface. MSB first, Active high strobe. Byte count on reception. 10, 8, 4, 2, 1 MHz and other programmable frequencies. TX, RX, Programmable Almost Full and Programmable Almost Empty interrupts. Use to interface with Receivers, Antenna Control Units and other serial interface equipment.

    BiSerial version PA1
    Customer: Phillips Aerospace
    Complex state machine with programmable delays for Frame to Word, Word to Data, data to Word, Inter-Word gap and Word to Frame. Odd or Even Parity generation and checking. FRAME, WORD, DATA and CLOCK interface signals. PAE and PAF interrupts. Three and Four wire modes. Frame, Parity and overrun error checking on input channel. Transitions on the rising edge, valid data on the falling edge. Can be programmed to use an internal reference clock at multiple frequencies or the external reference clock. Timing diagrams available in the manual.

    BiSerial version RTN1
    Customer: Raytheon
    RTN1 features a 10 MHz serial data rate with programmable clock and special handshaking features. Timing diagrams available in the manual. PDF link to the manual at the bottom of this page.

    BiSerial version RTN2
    Customer: Raytheon
    RTN2 is an update to BA2 with an expanded word counter, 16 Mb FIFO, programmable parity odd/even and on/off, programmable almost empty and programmable almost full interrupt capabilities added. IP, oscillator or user clock reference with 12 bit programmable divider for transmit frequencies. Timing diagram available in the manual. PDF link to the manual at the bottom of this page.

    BiSerial version LS1
    Customer: DERA / Land Systems
    LS1 features 4 MHz serial data rate with data, clock and strobe interface. Full Transmit and Receive Channels. 16K FIFOs both channels. TX/RX complete interrupts plus PAE and PAF. Timing diagrams available in the manual. PDF link to the manual at the bottom of this page.


    BiSerial version NG2
    Customer: Northrop Grumman
    The NG2 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP Clock or on-board oscillator [4.096 MHz] is used to derive the reference clocks for serial operation. A range of frequencies is available; 512KHz. is the base design frequency. Frame and Word sync plus the synchronous clock signals control data flow. 32 bit data with parity. MSB first, parity last. Parity, Frame, Over-run checked on the receive channel. Parity generated on the transmit channel. Programmable received word count. Programmable timing characteristics on Frame and Word sync: Frame asserted, Frame to Word, inter-word gap. Programmable active edge of clock. Multiple interrupt options.


    BiSerial version NG4
    Customer: Northrop Grumman
    The NG4 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP Clock or on-board oscillator [50 MHz] is used to derive the reference clocks for serial operation. A range of frequencies is available. The NG4 is an upgrade to the NG2 with a 3 and a 4 wire mode.

    In 4 wire mode [NG2]Frame and Word sync plus the synchronous clock signals control data flow. 32 bit data with parity. MSB first, parity last. Programmable Parity, Frame, Over-run checked on the receive channel. Parity generated on the transmit channel. Programmable received word count or "receive all" mode. Programmable timing characteristics on Frame and Word sync: Frame asserted, Frame to Word, inter-word gap. Programmable active edge of clock. Multiple interrupt options. In 3 wire mode the Frame Sync is ignored on the receiver.


    BiSerial version Q1
    Customer: QinetiQ
    The Q1 version of the BiSerial board supports both 8 and 32 MHz IP Bus operation. The IP Clock is used to derive the reference clocks for serial operation. A range of frequencies is available; 62.5 KHz. is the base design frequency. Bursted clock and data. signals control data flow. 16 bit data with parity. LSB first, parity last. Single or double word transmissions. Parity and Over-run checked on the receive channel. Parity generated on the transmit channel. Programmable 16/32 bit operation and continuous mode. Multiple interrupt options. 1K x 16 FIFO buffers. Windows® XP/2000 and Linux Drivers available.


    BiSerial version Miller
    Customer: Nakano Science and Engineering
    The Miller version of the BiSerial board implements the "Miller" encoding and decoding scheme. The Miller method uses transitions and spacing to encode/decode data. The result is a 50% [overall] duty cycle waveform with clock and data in the same data stream. The Miller version supports both transmit and receive operation, TTL and 485 IO [software selectable] plus the usual IP-BiSerial features. 8K x 16 FIFO buffers. Windows® XP/2000 Driver available. Please refer to the data page for more information. The manuals are available below.

    Manuals
    You must have Adobe Acrobat 4.x to read our PDF files.

    IP-BiSerial-IO manual PDF Revision A3

    IP-BiSerial-BA1 Rev A manual PDF

    IP-BiSerial-BA2 Rev A2 manual PDF

    IP-BiSerial-BA3 Rev A2 manual PDF

    IP-BiSerial-BA4 Rev A manual PDF

    IP-BiSerial-BA5 Rev A manual PDF

    IP-BiSerial-BA13 RevB manual PDF

    IP-BiSerial-HDP Rev C manual PDF

    IP-BiSerial-PA1 Rev A2 manual PDF

    IP-BiSerial-RTN1 manual PDF

    IP-BiSerial-RTN2 manual PDF

    IP-BiSerial-LS1 manual PDF

    IP-BiSerial-LM1 manual PDF

    IP-BiSerial-NG2 manual PDF

    IP-BiSerial-NG4 manual PDF

    IP-BiSerial-Q1 manual PDF
    IP-BiSerial-Q1 XP/2000 driver interface manual PDF
    IP-BiSerial-Q1 Linux driver interface manual PDF

    IP-BiSerial-Miller manual PDF
    IP-BiSerial-Miller XP/2000 driver interface manual PDF


    Try before you buy program
    Custom, IP, PMC, XMC, PCI, cPCI, VME, VPX, PC104p Hardware, Software designed to your requirements



    Home | News | Search the Dynamic Engineering Site